LEADER 05301nam 22006975 450 001 9910299665503321 005 20230118152603.0 010 $a1-4614-0821-0 024 7 $a10.1007/978-1-4614-0821-5 035 $a(CKB)3710000000277375 035 $a(EBL)1964792 035 $a(OCoLC)894893242 035 $a(SSID)ssj0001386254 035 $a(PQKBManifestationID)11883478 035 $a(PQKBTitleCode)TC0001386254 035 $a(PQKBWorkID)11373793 035 $a(PQKB)10814544 035 $a(DE-He213)978-1-4614-0821-5 035 $a(MiAaPQ)EBC1964792 035 $a(PPN)183085078 035 $a(EXLCZ)993710000000277375 100 $a20141107d2015 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aMulti-Net Optimization of VLSI Interconnect$b[electronic resource] /$fby Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer 205 $a1st ed. 2015. 210 1$aNew York, NY :$cSpringer New York :$cImprint: Springer,$d2015. 215 $a1 online resource (245 p.) 300 $aDescription based upon print version of record. 311 1 $a1-4614-0820-2 320 $aIncludes bibliographical references and index. 327 $aAn Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization. 330 $aThis book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  ? Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; ? Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; ? Includes mathematical properties and conditions for optimality of layout, describes and analyses algorithmic solutions, and supplements analysis with examples taken from state-of-the-art chips. This book addresses an intriguing engineering challenge, namely the design of an enormous maze of wires, which run in about a dozen metal layers above billions of transistors in a modern processor. The physical insight, mathematical rigor and methodological approach described in the book, are essential for engineers and computer architects, as they develop new systems of ever-increasing complexity and migrate them to new generations of device technologies.  The Authors of this book didn?t only develop the academic methodologies, but actually developed CAD tools, and implemented their tools and methodologies to design VLSI chips. I had the privilege to work with them. --Mooly Eden, Senior Vice President, Intel Corporation; President, Intel Israel The speed, power, area, and reliability of high performance integrated circuits are determined by the on-chip interconnect. With the publication of this book, an important niche has been filled; that is local and global on-chip interconnect optimization. This book provides a theoretical basis for the practical design of the key issue in modern integrated circuits, the on-chip interconnect. --Eby G. Friedman, Distinguished Professor, University of Rochester. 606 $aElectronic circuits 606 $aElectronics 606 $aMicroelectronics 606 $aMicroprocessors 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 615 0$aElectronic circuits. 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aMicroprocessors. 615 14$aCircuits and Systems. 615 24$aElectronics and Microelectronics, Instrumentation. 615 24$aProcessor Architectures. 676 $a004.1 676 $a620 676 $a621.381 676 $a621.3815 700 $aMoiseev$b Konstantin$4aut$4http://id.loc.gov/vocabulary/relators/aut$0739754 702 $aKolodny$b Avinoam$4aut$4http://id.loc.gov/vocabulary/relators/aut 702 $aWimer$b Shmuel$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910299665503321 996 $aMulti-Net Optimization of VLSI Interconnect$92526413 997 $aUNINA