LEADER 04754nam 22006975 450 001 9910299664003321 005 20221013123154.0 010 $a3-319-01997-X 024 7 $a10.1007/978-3-319-01997-0 035 $a(CKB)3710000000261999 035 $a(EBL)1965111 035 $a(OCoLC)894042300 035 $a(SSID)ssj0001372473 035 $a(PQKBManifestationID)11895546 035 $a(PQKBTitleCode)TC0001372473 035 $a(PQKBWorkID)11304514 035 $a(PQKB)10411982 035 $a(DE-He213)978-3-319-01997-0 035 $a(MiAaPQ)EBC1965111 035 $a(PPN)182091813 035 $a(EXLCZ)993710000000261999 100 $a20141014d2015 u| 0 101 0 $aeng 135 $aur|n||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$aFlip-Flop Design in Nanometer CMOS$b[electronic resource] $eFrom High Speed to Low Energy /$fby Massimo Alioto, Elio Consoli, Gaetano Palumbo 205 $a1st ed. 2015. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2015. 215 $a1 online resource (268 p.) 300 $aDescription based upon print version of record. 311 1 $a3-319-01996-1 320 $aIncludes bibliographical references and index. 327 $aThe Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies. 330 $aThis book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate  and postgraduate students (already familiar with digital circuits and timing). ? Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems ? Offers in-depth analysis of the impact of nanometer effects on  design tradeoffs ? Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits ? Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop  . 606 $aElectronic circuits 606 $aMicroprocessors 606 $aNanotechnology 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aElectronic Circuits and Devices$3https://scigraph.springernature.com/ontologies/product-market-codes/P31010 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aNanotechnology and Microengineering$3https://scigraph.springernature.com/ontologies/product-market-codes/T18000 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aNanotechnology. 615 14$aCircuits and Systems. 615 24$aElectronic Circuits and Devices. 615 24$aProcessor Architectures. 615 24$aNanotechnology and Microengineering. 676 $a004.1 676 $a620 676 $a620.5 676 $a621.3815 700 $aAlioto$b Massimo$4aut$4http://id.loc.gov/vocabulary/relators/aut$0720587 702 $aConsoli$b Elio$4aut$4http://id.loc.gov/vocabulary/relators/aut 702 $aPalumbo$b Gaetano$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910299664003321 996 $aFlip-Flop Design in Nanometer CMOS$92507746 997 $aUNINA