LEADER 04127nam 22006495 450 001 9910299661303321 005 20200703193651.0 010 $a3-319-10569-8 024 7 $a10.1007/978-3-319-10569-7 035 $a(CKB)3710000000269640 035 $a(EBL)1965183 035 $a(SSID)ssj0001372452 035 $a(PQKBManifestationID)11732680 035 $a(PQKBTitleCode)TC0001372452 035 $a(PQKBWorkID)11319573 035 $a(PQKB)11211528 035 $a(DE-He213)978-3-319-10569-7 035 $a(MiAaPQ)EBC1965183 035 $a(PPN)182094340 035 $a(EXLCZ)993710000000269640 100 $a20141030d2015 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aAdvanced Hardware Design for Error Correcting Codes /$fedited by Cyrille Chavet, Philippe Coussy 205 $a1st ed. 2015. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2015. 215 $a1 online resource (197 p.) 300 $aDescription based upon print version of record. 311 $a3-319-10568-X 320 $aIncludes bibliographical references. 327 $aUser Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey.                                                                                                                                       . 330 $aThis book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book?s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. ? Examines how to optimize the architecture of hardware design for error correcting codes; ? Presents error correction codes from theory to optimized architecture for the current and the next generation standards; ? Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou. 606 $aElectronic circuits 606 $aElectrical engineering 606 $aComputers 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aCommunications Engineering, Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/T24035 606 $aInformation Systems and Communication Service$3https://scigraph.springernature.com/ontologies/product-market-codes/I18008 615 0$aElectronic circuits. 615 0$aElectrical engineering. 615 0$aComputers. 615 14$aCircuits and Systems. 615 24$aCommunications Engineering, Networks. 615 24$aInformation Systems and Communication Service. 676 $a005.7 676 $a620 676 $a621.3815 676 $a621.382 702 $aChavet$b Cyrille$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aCoussy$b Philippe$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a9910299661303321 996 $aAdvanced Hardware Design for Error Correcting Codes$91413062 997 $aUNINA