LEADER 03161oam  2200481   450 
001 9910299495603321
005 20190911112726.0
010   $a3-319-03659-9
024 7 $a10.1007/978-3-319-03659-5
035   $a(OCoLC)869553702
035   $a(MiFhGG)GVRL6WFB
035   $a(EXLCZ)993710000000078782
100   $a20140410d2014      uy             0
101 0 $aeng
135   $aurun|---uuuua
181   $ctxt
182   $cc
183   $acr
200 10$aNoise-shaping all-digital phase-locked loops $emodeling, simulation, analysis and design /$fFrancesco Brandonisio, Michael Peter Kennedy
205   $a1st ed. 2014.
210  1$aCham, Switzerland :$cSpringer,$d2014.
215   $a1 online resource (xiii, 177 pages) $cillustrations (some color)
225 1 $aAnalog Circuits and Signal Processing,$x1872-082X
300   $a"ISSN: 1872-082X."
300   $a"ISSN: 2197-1854 (electronic)."
311   $a3-319-03658-0 
320   $aIncludes bibliographical references at the end of each chapters and index.
327   $aIntroduction -- Phase Digitization in All-Digital PLLs -- A Unifying Framework for TDC Architectures -- Analytical Predictions of Phase Noise in ADPLLs -- Advantages of Noise Shaping and Dither -- Efficient Modeling and Simulation of Accumulator-Based ADPLLs -- Modelling and Estimating Phase Noise with Matlab.
330   $aThis book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.   ? Discusses in detail a wide range of all-digital phase-locked loops architectures; ? Presents a unified framework in which to model time-to-digital converters for ADPLLs; ? Explains a procedure to predict and simulate phase noise in oscillators and ADPLLs; ? Describes an efficient approach to model ADPLLS; ? Includes Matlab code to reproduce the examples in the book.
410  0$aAnalog circuits and signal processing.
606   $aPhase-locked loops
606   $aElectronic digital computers$xCircuits$xDesign and construction
615  0$aPhase-locked loops.
615  0$aElectronic digital computers$xCircuits$xDesign and construction.
676   $a621.3815364
700   $aBrandonisio$b Francesco$4aut$4http://id.loc.gov/vocabulary/relators/aut$0929393
702   $aKennedy$b Michael Peter
801  0$bMiFhGG
801  1$bMiFhGG
906   $aBOOK
912   $a9910299495603321
996   $aNoise-Shaping All-Digital Phase-Locked Loops$92088855
997   $aUNINA