LEADER 04215nam 22006615 450 001 9910299494503321 005 20200701170734.0 010 $a3-319-03221-6 024 7 $a10.1007/978-3-319-03221-4 035 $a(CKB)2670000000548027 035 $a(EBL)1698118 035 $a(OCoLC)880131982 035 $a(SSID)ssj0001186952 035 $a(PQKBManifestationID)11813525 035 $a(PQKBTitleCode)TC0001186952 035 $a(PQKBWorkID)11241454 035 $a(PQKB)10425904 035 $a(MiAaPQ)EBC1698118 035 $a(DE-He213)978-3-319-03221-4 035 $a(PPN)177821485 035 $a(EXLCZ)992670000000548027 100 $a20140321d2014 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aSystem Level ESD Protection$b[electronic resource] /$fby Vladislav Vashchenko, Mirko Scholz 205 $a1st ed. 2014. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2014. 215 $a1 online resource (331 p.) 300 $aDescription based upon print version of record. 311 $a3-319-03220-8 320 $aIncludes bibliographical references and index. 327 $aSystem 1 Level ESD design -- System Level Test Methods -- On-Chip System Level ESD Devices and Clamps -- Latch-up at System-Level Stress -- IC and Systemn ESD Co-Design. 330 $aThis book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection.  It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.   ? Provides a systematic approach for on-chip ESD protection design for system-level IC pins; ? Describes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structure; ? Includes a comprehensive description of wafer- level and component-level test methodologies and numerical simulations. 606 $aElectronic circuits 606 $aElectronics 606 $aMicroelectronics 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aElectronic Circuits and Devices$3https://scigraph.springernature.com/ontologies/product-market-codes/P31010 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 615 0$aElectronic circuits. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aCircuits and Systems. 615 24$aElectronic Circuits and Devices. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a620 676 $a621.381 676 $a621.3815 676 $a621.38152 700 $aVashchenko$b Vladislav$4aut$4http://id.loc.gov/vocabulary/relators/aut$0861062 702 $aScholz$b Mirko$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910299494503321 996 $aSystem Level ESD Protection$91921650 997 $aUNINA