LEADER 03040oam 2200481 450 001 9910299492803321 005 20190911112725.0 010 $a3-319-02378-0 024 7 $a10.1007/978-3-319-02378-6 035 $a(OCoLC)867640163 035 $a(MiFhGG)GVRL6VOU 035 $a(EXLCZ)993710000000074623 100 $a20131112d2014 uy 0 101 0 $aeng 135 $aurun|---uuuua 181 $ctxt 182 $cc 183 $acr 200 10$aDesign-for-test and test optimization techniques for TSV-based 3D stacked ICs /$fBrandon Noia, Krishnendu Chakrabarty ; foreword by Vishwani Agrawal 205 $a1st ed. 2014. 210 1$aCham, Switzerland :$cSpringer,$d2014. 215 $a1 online resource (xviii, 245 pages) $cillustrations (chiefly color) 225 0 $aGale eBooks 300 $aDescription based upon print version of record. 311 $a3-319-02377-2 320 $aIncludes bibliographical references. 327 $aIntroduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions. 330 $aThis book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain.  Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization.  Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.   ? Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; ? Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; ? Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  . 606 $aThree-dimensional integrated circuits 615 0$aThree-dimensional integrated circuits. 676 $a004.1 676 $a537.622 676 $a620 676 $a621.3815 700 $aNoia$b Brandon$4aut$4http://id.loc.gov/vocabulary/relators/aut$0882555 702 $aChakrabarty$b Krishnendu 702 $aAgrawal$b Vishwani D.$f1943- 801 0$bMiFhGG 801 1$bMiFhGG 906 $aBOOK 912 $a9910299492803321 996 $aDesign-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs$91971430 997 $aUNINA