LEADER 03716oam 2200517 450 001 9910299487803321 005 20190911103512.0 010 $a1-4614-8310-7 024 7 $a10.1007/978-1-4614-8310-6 035 $a(OCoLC)872698957 035 $a(MiFhGG)GVRL6XTO 035 $a(EXLCZ)993710000000024853 100 $a20130808d2014 uy 0 101 0 $aeng 135 $aurun|---uuuua 181 $ctxt 182 $cc 183 $acr 200 10$aTurbo decoder architecture for beyond-4G applications /$fCheng-Chi Wong, Hsie-Chia Chang 205 $a1st ed. 2014. 210 1$aNew York :$cSpringer,$d2014. 215 $a1 online resource (viii, 100 pages) $cillustrations 225 0 $aGale eBooks 300 $aDescription based upon print version of record. 311 $a1-4614-8309-3 320 $aIncludes bibliographical references. 327 $aIntroduction -- Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly Parallel Architecture. 330 $aThis book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications.  The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time.  Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. Several state-of-the-art techniques that improve complexity and/or throughput are introduced.  The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards and enables designs that reconfigure block size and parallelism.  Case studies include the discussions of both throughput and performance of each mode (block size/parallelism/iteration).  This book not only highlights the critical design issues that restrict the speedup of parallel architecture, but it also provides the solutions to overcome these limitations by modifying slightly the turbo codec of modern standards.     ·         Offers readers a complete introduction to practical turbo decoder design; ·         Describes different design methodologies and explains the trade-offs between performance improvement and overhead; ·         Explains modern techniques for state-of-the-art designs; ·         Includes simulation and implementation results with respect to various decoder circuit designs; ·         Reveals novel approaches to higher operating efficiency of turbo decoders for beyond 4G applications. 606 $aWireless communication systems 606 $aSignal processing$xDigital techniques 606 $aLong-Term Evolution (Telecommunications) 615 0$aWireless communication systems. 615 0$aSignal processing$xDigital techniques. 615 0$aLong-Term Evolution (Telecommunications) 676 $a004.1 676 $a620 676 $a621.3815 676 $a621.382 700 $aWong$b Cheng-Chi$4aut$4http://id.loc.gov/vocabulary/relators/aut$0871860 702 $aChang$b Hsie-Chia 801 0$bMiFhGG 801 1$bMiFhGG 906 $aBOOK 912 $a9910299487803321 996 $aTurbo Decoder Architecture for Beyond-4G Applications$91946419 997 $aUNINA