LEADER 00715nam0-2200253 --450 001 9910596600803321 005 20221020143835.0 010 $a9780712356688 100 $a20221020d2017----kmuy0itay5050----ba 101 0 $aeng 105 $a 001yy 200 1 $a<>art and history of calligraphy$fPatricia Lovett 210 1$aLondon$cThe British Library$d2017 215 $a224 p.$cill.$d28 cm 676 $a745.61 700 1$aLovett,$bPatricia$01233202 712 02$aBritish Library 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a9910596600803321 952 $a745.61 LOVP 01$b2021/4517$fFLFBC 959 $aFLFBC 996 $aArt and history of calligraphy$92921473 997 $aUNINA LEADER 02629oam 2200481 450 001 9910299477603321 005 20190911103512.0 010 $a1-4614-9405-2 024 7 $a10.1007/978-1-4614-9405-8 035 $a(OCoLC)867728112 035 $a(MiFhGG)GVRL6YTW 035 $a(EXLCZ)993710000000073413 100 $a20130927d2014 uy 0 101 0 $aeng 135 $aurun|---uuuua 181 $ctxt 182 $cc 183 $acr 200 10$aSource-synchronous networks-on-chip $ecircuit and architectural interconnect modeling /$fAyan Mandal, Sunil P. Khatri, Rabi Mahapatra 205 $a1st ed. 2014. 210 1$aNew York :$cSpringer,$d2014. 215 $a1 online resource (xiii, 143 pages) $cillustrations (some color) 225 0 $aGale eBooks 300 $aIncludes index. 311 $a1-4614-9404-4 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work. 330 $aThis book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   ? Describes novel methods for high-speed network-on-chip (NoC) design; ? Enables readers to understand NoC design from both circuit and architectural levels; ? Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; ? Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art. 606 $aNetworks on a chip$xDesign 615 0$aNetworks on a chip$xDesign. 676 $a004.1 676 $a620 676 $a621.381 676 $a621.3815 700 $aMandal$b Ayan$4aut$4http://id.loc.gov/vocabulary/relators/aut$0948384 702 $aKhatri$b Sunil P.$f1965- 702 $aMahapatra$b Rabi N. 801 0$bMiFhGG 801 1$bMiFhGG 906 $aBOOK 912 $a9910299477603321 996 $aSource-Synchronous Networks-On-Chip$92143761 997 $aUNINA