LEADER 03326oam  2200481   450 
001 9910299471103321
005 20190911112725.0
010   $a3-319-01113-8
024 7 $a10.1007/978-3-319-01113-4
035   $a(OCoLC)869378184
035   $a(MiFhGG)GVRL6VTV
035   $a(EXLCZ)993710000000074795
100   $a20130820d2014      uy             0
101 0 $aeng
135   $aurun|---uuuua
181   $ctxt
182   $cc
183   $acr
200 10$aPipelined multiprocessor system-on-chip for multimedia /$fHaris Javaid, Sri Parameswaran
205   $a1st ed. 2014.
210  1$aCham, Switzerland :$cSpringer,$d2014.
215   $a1 online resource (viii, 169 pages) $cillustrations (some color)
225 0 $aGale eBooks
300   $aDescription based upon print version of record.
311   $a3-319-01112-X 
320   $aIncludes bibliographical references and index.
327   $aIntroduction -- Literature Survey -- Optimisation Framework -- Performance Estimation of Pipelined MPSoCs -- Design Space Exploration of Pipelined MPSoCs -- Adaptive Pipelined MPSoCs -- Power Management in Adaptive Pipelined MPSocs -- Multi-mode Pipelined MPSoCs -- Conclusions and Future Work.
330   $aThis book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs).  A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint.  A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors? combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.   ·         Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCs; ·         Includes analytical models and estimation methods for performance estimation of pipelined MPSoCs; ·         Covers several design space exploration techniques for pipelined MPSoCs; ·         Introduces an adaptive pipelined MPSoC with run-time processor and power managers; ·         Introduces Multi-mode pipelined MPSoCs for multiple applications.    .
606   $aEmbedded computer systems$xDesign and construction
606   $aMultiprocessors
606   $aSystems on a chip
615  0$aEmbedded computer systems$xDesign and construction.
615  0$aMultiprocessors.
615  0$aSystems on a chip.
676   $a004.35
700   $aJavaid$b Haris$4aut$4http://id.loc.gov/vocabulary/relators/aut$0871298
702   $aParameswaran$b Sri$f1962-
801  0$bMiFhGG
801  1$bMiFhGG
906   $aBOOK
912   $a9910299471103321
996   $aPipelined Multiprocessor System-on-Chip for Multimedia$91945044
997   $aUNINA