LEADER 02304oam  2200457   450 
001 9910299470203321
005 20190911112725.0
010   $a3-319-02381-0
024 7 $a10.1007/978-3-319-02381-6
035   $a(OCoLC)864755537
035   $a(MiFhGG)GVRL6YEK
035   $a(EXLCZ)992550000001152828
100   $a20130918d2014      uy             0
101 0 $aeng
135   $aurun|---uuuua
181   $ctxt
182   $cc
183   $acr
200 10$aHigh-bandwidth memory interface /$fChulwoo Kim, Hyun-Woo Lee, Junyoung Song
205   $a1st ed. 2014.
210  1$aNew York :$cSpringer,$d2014.
215   $a1 online resource (viii, 88 pages) $cillustrations (some color)
225 1 $aSpringerBriefs in Electrical and Computer Engineering,$x2191-8112
300   $a"ISSN: 2191-8112."
311   $a3-319-02380-2 
320   $aIncludes bibliographical references and index.
327   $aAn introduction to high-speed DRAM -- An I/O Line Configuration and Organization of DRAM -- Clock generation and distribution -- Transceiver Design -- TSV Interface for DRAM.
330   $aThis book provides an overview of recent advances in memory interface design at both the architecture and circuit levels. Coverage includes signal integrity and testing, TSV interface, high-speed serial interface including equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew cancellation, and clock generation and distribution. Trends for further bandwidth enhancement are also covered.   ? Enables readers with minimal background in memory design to understand the basics of high-bandwidth memory interface design; ? Presents state-of-the-art techniques for memory interface design; ? Covers memory interface design at both the circuit level and system architecture level.
410  0$aSpringerBriefs in electrical and computer engineering.
606   $aComputer storage devices
615  0$aComputer storage devices.
676   $a621.398
700   $aKim$b Chulwoo$4aut$4http://id.loc.gov/vocabulary/relators/aut$0873959
702   $aLee$b Hyun-Woo
702   $aSong$b Junyoung
801  0$bMiFhGG
801  1$bMiFhGG
906   $aBOOK
912   $a9910299470203321
996   $aHigh-Bandwidth Memory Interface$91951212
997   $aUNINA