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010   $a3-319-94493-2
024 7 $a10.1007/978-3-319-94493-7
035   $a(CKB)4100000005679162
035   $a(MiAaPQ)EBC5491620
035   $a(DE-He213)978-3-319-94493-7
035   $a(PPN)229917518
035   $a(EXLCZ)994100000005679162
100   $a20180810d2018      u|         0
101 0 $aeng
135   $aurcnu||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aInterrupt Handling Schemes in Operating Systems /$fby Pedro Mejia-Alvarez, Luis Eduardo Leyva-del-Foyo, Arnaldo Diaz-Ramirez
205   $a1st ed. 2018.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2018.
215   $a1 online resource (59 pages)
225 1 $aSpringerBriefs in Computer Science,$x2191-5768
311   $a3-319-94492-4 
327   $a1. Interrupt Mechanism -- 2. Interrupt Handling in Classic Operating Systems -- 3. Handling of Interrupts as Threads -- 4. Interrupt Handling in Android -- 5. Treatment of Interrupts in Embedded and Real Time Systems -- 6. Interrupt Handling Architectures -- References.-.
330   $aIn this book, the interrupt handling models used by several operating systems are introduced and compared. We begin with an analysis of the classical interrupt management model used by Unix, followed by the schemes used by modern networked environments. We highlight the key challenges of each of these models and how these have been solved by modern operating systems and the research community. Then we analyze the architectures used for general purpose and embedded real-time operating systems.
410  0$aSpringerBriefs in Computer Science,$x2191-5768
606   $aComputer hardware
606   $aOperating systems (Computers)
606   $aMicroprocessors
606   $aComputer Hardware$3https://scigraph.springernature.com/ontologies/product-market-codes/I1200X
606   $aOperating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14045
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
615  0$aComputer hardware.
615  0$aOperating systems (Computers)
615  0$aMicroprocessors.
615 14$aComputer Hardware.
615 24$aOperating Systems.
615 24$aProcessor Architectures.
676   $a005.4469
700   $aMejia-Alvarez$b Pedro$4aut$4http://id.loc.gov/vocabulary/relators/aut$0954503
702   $aLeyva-del-Foyo$b Luis Eduardo$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aDiaz-Ramirez$b Arnaldo$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910299350703321
996   $aInterrupt Handling Schemes in Operating Systems$92158916
997   $aUNINA