LEADER 03687nam 22005295 450 001 9910254335203321 005 20200703001642.0 010 $a3-319-54714-3 024 7 $a10.1007/978-3-319-54714-5 035 $a(CKB)3710000001118046 035 $a(DE-He213)978-3-319-54714-5 035 $a(MiAaPQ)EBC4826524 035 $a(PPN)199770263 035 $a(EXLCZ)993710000001118046 100 $a20170320d2017 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aTesting of Interposer-Based 2.5D Integrated Circuits /$fby Ran Wang, Krishnendu Chakrabarty 205 $a1st ed. 2017. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2017. 215 $a1 online resource (XIV, 182 p. 118 illus., 102 illus. in color.) 311 $a3-319-54713-5 320 $aIncludes bibliographical references at the end of each chapters. 327 $aIntroduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.-. 330 $aThis book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. 606 $aElectronic circuits 606 $aMicroprocessors 606 $aLogic design 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aLogic Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I12050 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aLogic design. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aLogic Design. 676 $a621.3815 700 $aWang$b Ran$4aut$4http://id.loc.gov/vocabulary/relators/aut$0968451 702 $aChakrabarty$b Krishnendu$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910254335203321 996 $aTesting of Interposer-Based 2.5D Integrated Circuits$92199628 997 $aUNINA