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010   $a3-319-24004-8
024 7 $a10.1007/978-3-319-24004-6
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035   $a(EBL)4339807
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035   $a(PQKBTitleCode)TC0001606969
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035   $a(DE-He213)978-3-319-24004-6
035   $a(MiAaPQ)EBC4339807
035   $a(PPN)191699470
035   $a(EXLCZ)993710000000577025
100   $a20160118d2016      u|         0
101 0 $aeng
135   $aur|n|---|||||
181   $ctxt
182   $cc
183   $acr
200 10$aHeterogeneous Reconfigurable Processors for Real-Time Baseband Processing $eFrom Algorithm to Architecture /$fby Chenxin Zhang, Liang Liu, Viktor Öwall
205   $a1st ed. 2016.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2016.
215   $a1 online resource (203 p.)
300   $aDescription based upon print version of record.
311   $a3-319-24002-1 
320   $aIncludes bibliographical references at the end of each chapters.
327   $aIntroduction -- Digital Hardware Platforms -- Digital Baseband Processing -- The Reconfigurable Cell Array -- Multi-standard Digital Front-End Processing -- Multi-task MIMO Signal Processing -- Future Multi-user MIMO systems ? A Discussion -- Conclusion.-.
330   $aThis book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. ?Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfiguration; ?Describes a unique design and optimization methodology, applied to different areas and levels, including communication theory, hardware implementation, and software support; ?Demonstrates design trade-offs during different development phases and enables readers to apply similar techniques to various applications.
606   $aElectronic circuits
606   $aMicroprocessors
606   $aElectronics
606   $aMicroelectronics
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
606   $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027
615  0$aElectronic circuits.
615  0$aMicroprocessors.
615  0$aElectronics.
615  0$aMicroelectronics.
615 14$aCircuits and Systems.
615 24$aProcessor Architectures.
615 24$aElectronics and Microelectronics, Instrumentation.
676   $a620
700   $aZhang$b Chenxin$4aut$4http://id.loc.gov/vocabulary/relators/aut$0762259
702   $aLiu$b Liang$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aÖwall$b Viktor$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910254244803321
996   $aHeterogeneous Reconfigurable Processors for Real-Time Baseband Processing$92520210
997   $aUNINA