LEADER 03745nam 22005895 450 001 9910254193103321 005 20200702114300.0 010 $a3-319-23389-0 024 7 $a10.1007/978-3-319-23389-5 035 $a(CKB)3710000000515648 035 $a(EBL)4093072 035 $a(SSID)ssj0001584690 035 $a(PQKBManifestationID)16265128 035 $a(PQKBTitleCode)TC0001584690 035 $a(PQKBWorkID)14866333 035 $a(PQKB)10485655 035 $a(DE-He213)978-3-319-23389-5 035 $a(MiAaPQ)EBC4093072 035 $a(PPN)19052085X 035 $a(EXLCZ)993710000000515648 100 $a20151114d2016 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aNear Threshold Computing$b[electronic resource] $eTechnology, Methods and Applications /$fedited by Michael Hübner, Cristina Silvano 205 $a1st ed. 2016. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2016. 215 $a1 online resource (104 p.) 300 $aDescription based upon print version of record. 311 $a3-319-23388-2 320 $aIncludes bibliographical references. 327 $aPART I: NTC opportunities, challenges and limits -- Chapter 1: Extreme Energy Efficiency by Near Threshold Voltage Operation -- Part II Micro-architecture challenges and energy management at NTC -- Chapter2: Many-core Architecture for NTC: Energy Efficiency from the Ground Up -- Chapter 3: Variability-Aware Voltage Island Management for Near-Threshold Voltage Computing With Performance Guarantees -- Part III Memory system design for NTC -- Chapter4: Resizable Data Composer (RDC) Cache: A Near-Threshold Cache tolerating Process Variation Via architectural fault tolerance -- Chapter 5 Memories for NTC. 330 $aThis book explores near-threshold computing (NTC), a design-space using techniques to run digital chips (processors) near the lowest possible voltage.  Readers will be enabled with specific techniques to design chips that are extremely robust; tolerating variability and resilient against errors.  Variability-aware voltage and frequency allocation schemes will be presented that will provide performance guarantees, when moving toward near-threshold manycore chips.  ·         Provides an introduction to near-threshold computing, enabling reader with a variety of tools to face the challenges of the power/utilization wall; ·         Demonstrates how to design efficient voltage regulation, so that each region of the chip can operate at the most efficient voltage and frequency point; ·         Investigates how performance guarantees can be ensured when moving towards NTC manycores through variability-aware voltage and frequency allocation schemes.  . 606 $aElectronic circuits 606 $aMicroprocessors 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aElectronic Circuits and Devices$3https://scigraph.springernature.com/ontologies/product-market-codes/P31010 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronic Circuits and Devices. 676 $a620 702 $aHübner$b Michael$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aSilvano$b Cristina$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a9910254193103321 996 $aNear Threshold Computing$91547676 997 $aUNINA