LEADER 04181nam 22006855 450 001 9910254182703321 005 20200704015316.0 010 $a3-319-22035-7 024 7 $a10.1007/978-3-319-22035-2 035 $a(CKB)3710000000467434 035 $a(EBL)4178452 035 $a(SSID)ssj0001546797 035 $a(PQKBManifestationID)16141534 035 $a(PQKBTitleCode)TC0001546797 035 $a(PQKBWorkID)14796161 035 $a(PQKB)10125591 035 $a(DE-He213)978-3-319-22035-2 035 $a(MiAaPQ)EBC4178452 035 $a(PPN)188461655 035 $a(EXLCZ)993710000000467434 100 $a20150827d2016 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aIP Cores Design from Specifications to Production $eModeling, Verification, Optimization, and Protection /$fby Khaled Salah Mohamed 205 $a1st ed. 2016. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2016. 215 $a1 online resource (162 p.) 225 1 $aAnalog Circuits and Signal Processing,$x1872-082X 300 $aDescription based upon print version of record. 311 $a3-319-22034-9 320 $aIncludes bibliographical references at the end of each chapters. 327 $a1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions. 330 $aThis book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author?s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies. ·         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; ·         Introduce a deep introduction for Verilog for both implementation and verification point of view.  ·         Demonstrates how to use IP in applications such as memory controllers and SoC buses. ·         Describes a new verification methodology called bug localization; ·         Presents a novel scan-chain methodology for RTL debugging; ·         Enables readers to employ UVM methodology in straightforward, practical terms. 410 0$aAnalog Circuits and Signal Processing,$x1872-082X 606 $aElectronic circuits 606 $aMicroprocessors 606 $aElectronics 606 $aMicroelectronics 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a620 700 $aMohamed$b Khaled Salah$4aut$4http://id.loc.gov/vocabulary/relators/aut$0761899 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910254182703321 996 $aIP Cores Design from Specifications to Production$91543042 997 $aUNINA