LEADER 02301nam 2200493 450 001 9910821972703321 005 20230419165400.0 010 $a84-9116-720-X 035 $a(CKB)3790000000475818 035 $a(MiAaPQ)EBC4946060 035 $a(OCoLC)1105401084 035 $a(FlNmELB)ELB58633 035 $a(MiAaPQ)EBC7051745 035 $a(Au-PeEL)EBL7051745 035 $a(EXLCZ)993790000000475818 100 $a20230419d2017 uy 0 101 0 $aspa 135 $aurcnu|||||||| 181 $2rdacontent 182 $2rdamedia 183 $2rdacarrier 200 10$aFu?tbol, identidades y medios de comunicacio?n $ela imagen del FC Barcelona en la prensa deportiva Japonesa /$fJordi Juste Garrigo?s 210 1$aBarcelona :$cEditorial UOC,$d[2017] 210 4$d©2017 215 $a1 online resource (263 pa?ginas) 225 1 $aManuales Series 300 $aIncluye i?ndice. 311 $a84-9116-719-6 320 $aIncludes bibliographical references. 330 $aEl estudio de la imagen del Barça en Japón sirve para comprender tanto el alcance de la globalización del fútbol como la proyección de un club de un lejano país europeo en una gran nación asiática. La dimensión glocal del Barça se refleja en la cobertura de los diarios Nikkan Sports y Sponichi de las temporadas 2010-2011 y 2013-2014. El análisis cuantitativo y cualitativo de fotografías, titulares y cuerpos de textos revela la imagen positiva de un club español conocido como FC Barcelona y representado, sobre todo, por Leo Messi. El seguimiento de la entidad se centra en su vertiente deportiva: se concentra en la fase resolutiva de la temporada, en los acontecimientos decisivos de la competición y en su relación con Japón, e incluye una narrativa implícita plagada de metáforas y sin estereotipos. 410 0$aManuales (Editorial UOC) 606 $aSports journalism 606 $aMass media and sports 615 0$aSports journalism. 615 0$aMass media and sports. 676 $a796.334092 700 $aJuste Garrigo?s$b Jordi$01620475 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910821972703321 996 $aFu?tbol, identidades y medios de comunicacio?n$93953260 997 $aUNINA LEADER 03985nam 22006855 450 001 9910254182703321 005 20251023193424.0 010 $a3-319-22035-7 024 7 $a10.1007/978-3-319-22035-2 035 $a(CKB)3710000000467434 035 $a(EBL)4178452 035 $a(SSID)ssj0001546797 035 $a(PQKBManifestationID)16141534 035 $a(PQKBTitleCode)TC0001546797 035 $a(PQKBWorkID)14796161 035 $a(PQKB)10125591 035 $a(DE-He213)978-3-319-22035-2 035 $a(MiAaPQ)EBC4178452 035 $a(PPN)188461655 035 $a(EXLCZ)993710000000467434 100 $a20150827d2016 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aIP Cores Design from Specifications to Production $eModeling, Verification, Optimization, and Protection /$fby Khaled Salah Mohamed 205 $a1st ed. 2016. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2016. 215 $a1 online resource (162 p.) 225 1 $aAnalog Circuits and Signal Processing,$x2197-1854 300 $aDescription based upon print version of record. 311 08$a3-319-22034-9 320 $aIncludes bibliographical references at the end of each chapters. 327 $a1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions. 330 $aThis book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author?s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies. ·         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; ·         Introduce a deep introduction for Verilog for both implementation and verification point of view.  ·         Demonstrates how to use IP in applications such as memory controllers and SoC buses. ·         Describes a new verification methodology called bug localization; ·         Presents a novel scan-chain methodology for RTL debugging; ·         Enables readers to employ UVM methodology in straightforward, practical terms. 410 0$aAnalog Circuits and Signal Processing,$x2197-1854 606 $aElectronic circuits 606 $aMicroprocessors 606 $aComputer architecture 606 $aElectronics 606 $aElectronic Circuits and Systems 606 $aProcessor Architectures 606 $aElectronics and Microelectronics, Instrumentation 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aElectronics. 615 14$aElectronic Circuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a620 700 $aMohamed$b Khaled Salah$4aut$4http://id.loc.gov/vocabulary/relators/aut$0761899 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910254182703321 996 $aIP Cores Design from Specifications to Production$91543042 997 $aUNINA