LEADER 03763nam  22005655  450 
001 9910254167803321
005 20200701001503.0
010   $a3-319-42037-2
024 7 $a10.1007/978-3-319-42037-0
035   $a(CKB)3710000000765099
035   $a(DE-He213)978-3-319-42037-0
035   $a(MiAaPQ)EBC4617322
035   $a(PPN)194517241
035   $a(EXLCZ)993710000000765099
100   $a20160729d2017      u|         0
101 0 $aeng
135   $aurnn|008mamaa
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aAutomatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects /$fby Nuno Lourenço, Ricardo Martins, Nuno Horta
205   $a1st ed. 2017.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2017.
215   $a1 online resource (XXVII, 182 p. 112 illus., 90 illus. in color.) 
311   $a3-319-42036-4 
320   $aIncludes bibliographical references at the end of each chapters and index.
327   $aIntroduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions.
330   $aThis book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit?s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.
606   $aElectronic circuits
606   $aMicroprocessors
606   $aElectronics
606   $aMicroelectronics
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
606   $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027
615  0$aElectronic circuits.
615  0$aMicroprocessors.
615  0$aElectronics.
615  0$aMicroelectronics.
615 14$aCircuits and Systems.
615 24$aProcessor Architectures.
615 24$aElectronics and Microelectronics, Instrumentation.
676   $a621.3815
700   $aLourenço$b Nuno$4aut$4http://id.loc.gov/vocabulary/relators/aut$0720939
702   $aMartins$b Ricardo$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aHorta$b Nuno$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910254167803321
996   $aAutomatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects$92203571
997   $aUNINA