LEADER 03236nam 22005655 450 001 9910253965703321 005 20251113182213.0 010 $a3-319-30607-3 024 7 $a10.1007/978-3-319-30607-0 035 $a(CKB)3710000000602460 035 $a(EBL)4427537 035 $a(SSID)ssj0001653872 035 $a(PQKBManifestationID)16433792 035 $a(PQKBTitleCode)TC0001653872 035 $a(PQKBWorkID)14982788 035 $a(PQKB)11070840 035 $a(DE-He213)978-3-319-30607-0 035 $a(MiAaPQ)EBC4427537 035 $a(PPN)192219855 035 $a(EXLCZ)993710000000602460 100 $a20160225d2016 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aSoft Error Mechanisms, Modeling and Mitigation /$fby Selahattin Sayil 205 $a1st ed. 2016. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2016. 215 $a1 online resource (112 p.) 300 $aIncludes index. 311 08$a3-319-30606-5 327 $aIntroduction -- Mitigation of Single Event Effects -- Transmission Gate (TG) Based Soft Error Mitigation Methods -- Single Event Soft Error Mechanisms -- Modeling Single Event Crosstalk Noise in Nanometer Technologies -- Modeling of Single Event Coupling Delay and Speedup Effects -- Single Event Upset Hardening of Interconnects -- Soft-Error Aware Power Optimization -- Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation. 330 $aThis book introduces readers to various radiation soft-error mechanisms such as soft delays, radiation induced clock jitter and pulses, and single event (SE) coupling induced effects. In addition to discussing various radiation hardening techniques for combinational logic, the author also describes new mitigation strategies targeting commercial designs. Coverage includes novel soft error mitigation techniques such as the Dynamic Threshold Technique and Soft Error Filtering based on Transmission gate with varied gate and body bias. The discussion also includes modeling of SE crosstalk noise, delay and speed-up effects. Various mitigation strategies to eliminate SE coupling effects are also introduced. Coverage also includes the reliability of low power energy-efficient designs and the impact of leakage power consumption optimizations on soft error robustness. The author presents an analysis of various power optimization techniques, enabling readers to make design choices that reduce static power consumption and improve soft error reliability at the same time. . 606 $aElectronic circuits 606 $aMicroprocessors 606 $aComputer architecture 606 $aElectronic Circuits and Systems 606 $aProcessor Architectures 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 14$aElectronic Circuits and Systems. 615 24$aProcessor Architectures. 676 $a620 700 $aSayil$b Selahattin$4aut$4http://id.loc.gov/vocabulary/relators/aut$0763561 906 $aBOOK 912 $a9910253965703321 996 $aSoft Error Mechanisms, Modeling and Mitigation$91549329 997 $aUNINA