LEADER 00920nam0-22003131i-450- 001 990001481330403321 005 20001010 035 $a000148133 035 $aFED01000148133 035 $a(Aleph)000148133FED01 035 $a000148133 100 $a20001010d--------km-y0itay50------ba 101 0 $aeng 105 $aa---a---001yy 200 1 $aIndex herbariorum$ea guide to the location and contents of the world's public herbaria$fedited by J. Lanjouw 210 $aUtrecht$cInternational Association of Plant taxonomy$d1957 215 $a120 p. 225 1 $aIndex Herbariorum$v2$f2 300 $aPart II(2). Lettera E-H. 610 0 $aTassonomia vegetale 702 1$aLanjouw,$bJoseph 702 1$aStafleu,$bF.A. 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990001481330403321 952 $aERBARIO E-H$b$fDBV 959 $aDBV 996 $aIndex herbariorum$9378335 997 $aUNINA LEADER 01950oam 2200469I 450 001 9910154587703321 005 20230808200638.0 010 $a1-351-88432-8 010 $a1-315-23786-5 024 7 $a10.4324/9781315237862 035 $a(CKB)3710000000965348 035 $a(MiAaPQ)EBC4758315 035 $a(OCoLC)973026718 035 $a(EXLCZ)993710000000965348 100 $a20180706d20161981 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $2rdacontent 182 $2rdamedia 183 $2rdacarrier 200 14$aThe phantom capitalists $ethe organization and control of long-firm fraud /$fMichael Levi 205 $aRevised edition. 210 1$aLondon :$cRoutledge,$d2016. 215 $a1 online resource (441 pages) $cillustrations, tables 300 $aFirst published 1981 by Heinemann. Published 2008 by Ashgate Publishing. 311 $a0-7546-4516-9 311 $a1-351-88433-6 320 $aIncludes bibliographical references and index. 327 $aI. Introduction -- II. History of long-firm fraud in England -- III. Craft of the long-firm fraudster -- IV. Social and criminal organisation of long-firm fraud -- V. Motivations and criminal careers of long-frim fraudsters -- IV. Informal control of long-firm fraud -- VII. Long-firm fraud and the criminal law -- VIII. Policing of long-firm fraud -- IX. Prosecution and trial of long-firm fraudsters -- X. Sentencing of long-firm fraudsters -- XI. Towards a theory of long-firm fraud -- XII. Control of long-firm fraud : some issues for the future. 606 $aCommercial crimes$zGreat Britain 606 $aFraud$zGreat Britain 615 0$aCommercial crimes 615 0$aFraud 676 $a364.16/30941 700 $aLevi$b Michael$0960977 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910154587703321 996 $aThe phantom capitalists$92210822 997 $aUNINA LEADER 03350nam 22005655 450 001 9910299951203321 005 20200705054549.0 010 $a3-319-75465-3 024 7 $a10.1007/978-3-319-75465-9 035 $a(CKB)4100000003359397 035 $a(MiAaPQ)EBC5355955 035 $a(DE-He213)978-3-319-75465-9 035 $a(PPN)22669688X 035 $a(EXLCZ)994100000003359397 100 $a20180418d2018 u| 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aTiming Performance of Nanometer Digital Circuits Under Process Variations /$fby Victor Champac, Jose Garcia Gervacio 205 $a1st ed. 2018. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2018. 215 $a1 online resource (195 pages) 225 1 $aFrontiers in Electronic Testing,$x0929-1296 ;$v39 311 $a3-319-75464-5 327 $aIntroduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues. 330 $aThis book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level ?design hints? are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability. 410 0$aFrontiers in Electronic Testing,$x0929-1296 ;$v39 606 $aElectronic circuits 606 $aMicroprocessors 606 $aElectronics 606 $aMicroelectronics 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a621.381 700 $aChampac$b Victor$4aut$4http://id.loc.gov/vocabulary/relators/aut$01062007 702 $aGarcia Gervacio$b Jose$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910299951203321 996 $aTiming Performance of Nanometer Digital Circuits Under Process Variations$92521983 997 $aUNINA