LEADER 01603nam 2200361 450 001 9910147236603321 005 20171005075426.0 035 $a(CKB)1000000000035597 035 $a(WaSeSS)IndRDA00078313 035 $a(NjHacI)991000000000035597 035 $a(EXLCZ)991000000000035597 100 $a20171005d2002 || | 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 00$aIEEE standard for a control and status registers (CSR) architecture for microcomputer buses 210 1$aNew York :$cIEEE,$d2002. 215 $a1 online resource (67 pages) 311 $a0-7381-3100-8 330 $aA common bus architecture (which includes functional components - modules, nodes, and units - and their address space, transaction set, CSRs, and configuration information) suitable for both parallel and serial buses is provided in this standard. Bus bridges are enabled by the architecture, but their details are beyond its scope. Configuration information is self-administered by vendors and organizations based upon IEEE Registration Authority company_id. 606 $aMicrocomputers$xBuses$xStandards 606 $aComputer architecture$xStandards 615 0$aMicrocomputers$xBuses$xStandards. 615 0$aComputer architecture$xStandards. 676 $a004.16 801 0$bWaSeSS 801 1$bWaSeSS 906 $aDOCUMENT 912 $a9910147236603321 996 $aIEEE standard for a control and status registers (CSR) architecture for microcomputer buses$92576485 997 $aUNINA