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101 0 $aeng
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181   $ctxt$2rdacontent
182   $cc$2rdamedia
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200 00$aIEEE standard for VHDL register transfer level (RTL) synthesis
210  1$aNew York :$cIEEE,$d2004.
215   $a1 online resource (112 pages)
311   $a0-7381-4065-1 
330   $aThis document specifies a standard for use of very high-speed integrated circuit hardwaredescription language (VHDL) to model synthesizable register-transfer level digital logic. Astandard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset ofthe VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructsare identified that should be ignored or flagged as errors.
606   $aVHDL (Computer hardware description language)$xStandards
606   $aComputer hardware description languages$xStandards
615  0$aVHDL (Computer hardware description language)$xStandards.
615  0$aComputer hardware description languages$xStandards.
676   $a621.392
712 02$aInstitute of Electrical and Electronics Engineers,
712 02$aAmerican National Standards Institute,
712 02$aIEEE-SA Standards Board,
801  0$bWaSeSS
801  1$bWaSeSS
906   $aDOCUMENT
912   $a9910147232003321
996   $aIEEE standard for VHDL register transfer level (RTL) synthesis$92576459
997   $aUNINA