LEADER 02128oam 2200421zu 450 001 9910146730503321 005 20241212215523.0 010 $a9781509088706 010 $a1509088709 035 $a(CKB)1000000000524880 035 $a(SSID)ssj0000781051 035 $a(PQKBManifestationID)12367090 035 $a(PQKBTitleCode)TC0000781051 035 $a(PQKBWorkID)10803894 035 $a(PQKB)10561118 035 $a(NjHacI)991000000000524880 035 $a(EXLCZ)991000000000524880 100 $a20160829d2007 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 00$a2007 IEEE International Conf on Application-specific Systems, Architectures and Processors (ASAP) 210 31$a[Place of publication not identified]$cIEEE$d2007 215 $a1 online resource 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9781424410262 311 08$a1424410266 330 $aThe Logarithmic Number System (LNS) makes multiplication, division and powering easy, but subtraction is expensive. Cotransformation converts the difficult operation of logarithmic subtraction into the easier operation of logarithmic addition. In this paper, a new variant of cotransformation is proposed, which is simpler to design and more economical in hardware than previous cotransformation methods. The novel method commutes operands differently for addition than for subtraction. Simulation results show how many guard bits are required by the new cotransformation to guarantee faithful rounding and that, even without guard bits, cotransformation produces an LNS unit more accurate than a previously published Hardware-Description-Language (HDL) library for LNS arithmetic that uses only multipartite tables or 2nd-order interpolation. 606 $aArray processors$vCongresses 615 0$aArray processors 676 $a004.16 801 0$bPQKB 906 $aPROCEEDING 912 $a9910146730503321 996 $a2007 IEEE International Conf on Application-specific Systems, Architectures and Processors (ASAP)$92415298 997 $aUNINA