LEADER 02482oam 2200601zu 450 001 9910146065603321 005 20210731015514.0 010 $a1-280-55652-8 010 $a9786610556526 010 $a0-471-45755-8 010 $a0-470-35692-8 010 $a0-471-45756-6 035 $a(CKB)1000000000019044 035 $a(SSID)ssj0000312670 035 $a(PQKBManifestationID)11229677 035 $a(PQKBTitleCode)TC0000312670 035 $a(PQKBWorkID)10332405 035 $a(PQKB)11500319 035 $a(CaSebORM)9780471429760 035 $a(MiAaPQ)EBC4957239 035 $a(Au-PeEL)EBL4957239 035 $a(CaONFJC)MIL55652 035 $a(OCoLC)1024270416 035 $a(EXLCZ)991000000000019044 100 $a20160829d2003 uy 101 0 $aeng 135 $aurunu||||| 181 $ctxt 182 $cc 183 $acr 200 10$aVerilog Coding for Logic Synthesis 205 $a1st edition 210 31$a[Place of publication not identified]$cWiley Interscience Imprint$d2003 215 $a1 online resource (1 v.) $cill 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a0-471-42976-7 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface. 330 $aProvides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. Book is suitable for use as a textbook in EE departments that have VLSI courses 606 $aDigital electronics 606 $aLogic circuits$xComputer-aided design 606 $aVerilog (Computer hardware description language) 608 $aElectronic books. 615 0$aDigital electronics. 615 0$aLogic circuits$xComputer-aided design. 615 0$aVerilog (Computer hardware description language) 676 $a621.395 700 $aLee$b Weng Fook$0867193 801 0$bPQKB 906 $aBOOK 912 $a9910146065603321 996 $aVerilog Coding for Logic Synthesis$92068017 997 $aUNINA LEADER 01673nam 2200469Ia 450 001 9910709939703321 005 20180711120937.0 024 8 $aGOVPUB-C13-57945e9171037a388a591478987ddb09 035 $a(CKB)5470000002474871 035 $a(OCoLC)124074582 035 $a(OCoLC)995470000002474871 035 $a(EXLCZ)995470000002474871 100 $a20070509d2004 ua 0 101 0 $aeng 135 $aurcn||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 00$aModel solid sample burning with FDS /$fGregory T Linteris, Llyod Gewuerz, Kevin McGrattan, Glenn Forney 210 1$a[Gaithersburg, MD] :$cU.S. Dept. of Commerce, National Institute of Standards and Technology,$d[2004]. 215 $a1 online resource (37 pages) $cillustrations 225 1 $aNISTIR ;$v7178 300 $a"October 2004." 300 $aContributed record: Metadata reviewed, not verified. Some fields updated by batch processes. 300 $aTitle from page [1], viewed April 6, 2007. 320 $aIncludes bibliographical references. 606 $aFire$xData processing$xComputer simulation 615 0$aFire$xData processing$xComputer simulation. 701 $aForney$b Glenn P$01381056 701 $aGewuerz$b Lloyd$01405313 701 $aLinteris$b Gregory T$01395371 701 $aMcGrattan$b Kevin B$01381055 712 02$aBuilding and Fire Research Laboratory (U.S.) 801 0$bNBS 801 1$bNBS 801 2$bOCLCQ 801 2$bOCLCO 801 2$bOCLCQ 906 $aBOOK 912 $a9910709939703321 996 $aModel solid sample burning with FDS$93481525 997 $aUNINA