LEADER 03647oam 2200445zu 450 001 9910145456903321 005 20241212215416.0 010 $a9781509099825 010 $a1509099824 035 $a(CKB)1000000000278028 035 $a(SSID)ssj0000396086 035 $a(PQKBManifestationID)12111761 035 $a(PQKBTitleCode)TC0000396086 035 $a(PQKBWorkID)10464869 035 $a(PQKB)10259984 035 $a(NjHacI)991000000000278028 035 $a(EXLCZ)991000000000278028 100 $a20160829d2005 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 00$a2005 international conference on reconfigurable computing and FPGAS 210 31$a[Place of publication not identified]$cIEEE Computer Society$d2005 215 $a1 online resource (183 pages) $cillustrations 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9780769524566 311 08$a0769524567 327 $aReal-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling, -- An image comparison circuit design," -- FPGA-based customizable systolic architecture for image processing applications," -- An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method," -- Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform," -- A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays," -- Rapid prototyping of a self-timed ALU with FPGAs," -- FPGA implementation of a synchronous and self-timed neuroprocessor," -- On the design of two-level reconfigurable architectures," -- A secure self-reconfiguring architecture based on open-source hardware," -- Platform for intrinsic evolution of analogue neural networks," -- High quality uniform random number generation for massively parallel simulations in FPGA," -- VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks," -- Quartz: a framework for correct and efficient reconfigurable design," -- Design space exploration of coarse-grain reconfigurable DSPs," -- Optimizing register binding in FPGAs using simulated annealing," -- An FPGA-based parallel sorting architecture for the Burrows Wheeler transform," -- Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices," -- Applied VHDL training methodology, EDA framework and hardware implementation platform," -- FPGA implementation of DSVPWM modulator," -- A novel FPGA implementation of a welding control using a new bus architecture," -- On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004," -- Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3," -- VHDL core for 1024-point radix-4 FFT computation," -- Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation," -- FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)," -- An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences," -- Hardware/software implementation of a discrete cosine transform algorithm using SystemC. 606 $aAdaptive computing systems$vCongresses 615 0$aAdaptive computing systems 676 $a004 702 $aFeregrino$b Claudia 702 $aCumplido$b Rene? 801 0$bPQKB 906 $aPROCEEDING 912 $a9910145456903321 996 $a2005 international conference on reconfigurable computing and FPGAS$92364582 997 $aUNINA