LEADER 01985oam  2200457zu 450 
001 9910145114803321
005 20210807003135.0
010   $a1-5090-8649-8
010   $a1-4244-1342-7
035   $a(CKB)1000000000698123
035   $a(SSID)ssj0000454206
035   $a(PQKBManifestationID)12203037
035   $a(PQKBTitleCode)TC0000454206
035   $a(PQKBWorkID)10396624
035   $a(PQKB)11407619
035   $a(NjHacI)991000000000698123
035   $a(EXLCZ)991000000000698123
100   $a20160829d2007      uy 
101 0 $aeng
135   $aur|||||||||||
181   $ctxt
182   $cc
183   $acr
200 00$a2007 European Conference on Circuit Theory and Design
210 31$a[Place of publication not identified]$cI E E E$d2007
215   $a1 online resource
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a1-4244-1341-9 
330   $a3D discrete wavelet transform (DWT) is a compute-intensive task that is usually implemented on specific architectures in many real-time medical imaging systems. In this paper, a novel area-efficient high-throughput 3D DWT architecture is proposed based on distributed arithmetic. A tap-merging technique is used to reduce the size of DA lookup tables. The proposed architectures were designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The synthesis results show the proposed architecture has a low area cost and can run up to 85 MHz, which can perform a five-level 3D wavelet analysis for seven 128 times 128 times 128 volume images per second.
606   $aElectric circuits$vCongresses
606   $aElectric filters$vCongresses
606   $aElectric networks$vCongresses
615  0$aElectric circuits
615  0$aElectric filters
615  0$aElectric networks
676   $a621.3192
801  0$bPQKB
906   $aPROCEEDING
912   $a9910145114803321
996   $a2007 European Conference on Circuit Theory and Design$92501857
997   $aUNINA