LEADER 07430nam 22007695 450 001 9910144916003321 005 20200702052108.0 010 $a3-540-69557-5 024 7 $a10.1007/3-540-63465-7 035 $a(CKB)1000000000234711 035 $a(SSID)ssj0000323125 035 $a(PQKBManifestationID)11242973 035 $a(PQKBTitleCode)TC0000323125 035 $a(PQKBWorkID)10296895 035 $a(PQKB)11464717 035 $a(DE-He213)978-3-540-69557-8 035 $a(PPN)155192132 035 $a(EXLCZ)991000000000234711 100 $a20121227d1997 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aField Programmable Logic and Applications$b[electronic resource] $e7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. /$fedited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner 205 $a1st ed. 1997. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d1997. 215 $a1 online resource (XII, 512 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v1304 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-63465-7 327 $aMulticontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor -- CAD-oriented FPGA and dedicated CAD system for telecommunications -- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools -- Extending dynamic circuit switching to meet the challenges of new FPGA architectures -- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs -- Implementation of pipelined multipliers on Xilinx FPGAs -- The XC620ODS development system -- Thermal monitoring on FPGAs using ring-oscillators -- A reconfigurable approach to low cost media processing -- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research -- Stream synthesis for a wormhole run-time reconfigurable platform -- Pipeline morphing and virtual pipelines -- Parallel graph colouring using FPGAs -- Run-time compaction of FPGA designs -- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement -- A case study of partially evaluated hardware circuits: Key-specific DES -- Run-time parameterised circuits for the Xilinx XC6200 -- Automatic identification of swappable logic units in XC6200 circuitry -- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic -- Exploiting reconfigurability through domain-specific systems -- Technology mapping by binate covering -- VPR: a new packing, placement and routing tool for FPGA research -- Technology mapping of heterogeneous LUT-based FPGAs -- Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs -- Technology mapping of LUT based FPGAs for delay optimisation -- Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules -- FPLD HDL synthesis employing high-level evolutionary algorithm optimisation -- An hardware/software partitioning algorithm for custom computing machines -- The Java Environment for Reconfigurable Computing -- Data scheduling to increase performance of parallel accelerators -- An operating system for custom computing machines based on the Xputer paradigm -- Fast parallel implementation of DFT using configurable devices -- Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elements -- A case study of algorithm implementation in reconfigurable hardware and software -- A reconfigurable data-localised array for morphological algorithms -- Virtual radix array processors (V-RaAP) -- An FPGA implementation of a matched filter detector for spread spectrum communications systems -- An NTSC and PAL closed caption processor -- A 800Mpixel/sec reconfigurable image correlator on XC6216 -- A reconfigurable coprocessor for a PCI-based real time computer vision system -- Real-time stereopsis using FPGAs -- FPGAs Implementation of a digital IQ demodulator using VHDL -- Hardware compilation, configurable platforms and ASICs for self-validating sensors -- PostScript? rendering with virtual hardware -- P4: A platform for FPGA implementation of protocol boosters -- Satisfiability on reconfigurable hardware -- Auto-configurable array for GCD computation -- Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA -- FPGA implementation of real-time digital controllers using on-line arithmetic -- A prototyping environment for fuzzy controllers -- A reconfigurable sensor-data processing system for personal robots. 330 $aThis book constitutes the refereed proceedings of the 7th International Workshop on Field Programmable Logic and Applications, FPL '97, held in London, UK, in September 1997. The 51 revised full papers in the volume were carefully selected from a large number of high-quality papers. The book is divided into sections on devices and architectures, devices and systems, reconfiguration, design tools, custom computing and codesign, signal processing, image and video processing, sensors and graphics, color and robotics, and applications. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v1304 606 $aComputer engineering 606 $aComputer architecture 606 $aProgramming languages (Electronic computers) 606 $aComputer hardware 606 $aComputational complexity 606 $aLogic, Symbolic and mathematical 606 $aComputer Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I27000 606 $aComputer System Implementation$3https://scigraph.springernature.com/ontologies/product-market-codes/I13057 606 $aProgramming Languages, Compilers, Interpreters$3https://scigraph.springernature.com/ontologies/product-market-codes/I14037 606 $aComputer Hardware$3https://scigraph.springernature.com/ontologies/product-market-codes/I1200X 606 $aComplexity$3https://scigraph.springernature.com/ontologies/product-market-codes/T11022 606 $aMathematical Logic and Formal Languages$3https://scigraph.springernature.com/ontologies/product-market-codes/I16048 615 0$aComputer engineering. 615 0$aComputer architecture. 615 0$aProgramming languages (Electronic computers) 615 0$aComputer hardware. 615 0$aComputational complexity. 615 0$aLogic, Symbolic and mathematical. 615 14$aComputer Engineering. 615 24$aComputer System Implementation. 615 24$aProgramming Languages, Compilers, Interpreters. 615 24$aComputer Hardware. 615 24$aComplexity. 615 24$aMathematical Logic and Formal Languages. 676 $a621.39/5 702 $aLuk$b Wayne$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aCheung$b Peter Y.K$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aGlesner$b Manfred$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aInternational Workshop on Field-Programmable Logic and Applications$d(7th :$f1997 :$eLondon, England) 906 $aBOOK 912 $a9910144916003321 996 $aField-programmable logic and applications$92106948 997 $aUNINA