LEADER 00787cac0 22002291 450 001 LAEC00020407 005 20151211154415.0 100 $a20110502f0000 |||||ita|0103 ba 102 $aIT 110 $ab 200 1 $aSubstantia 210 $aNapoli$cAlós 801 0$aIT$bUNISOB$c20151211$gRICA 912 $aLAEC00020407 940 $aC 121 Collana SBN 941 $aC 996 $aSubstantia$91696802 997 $aUNISOB 998 \\$1001E600200003881$12001 $aLettera apologetica 998 \\$1001E600200063429$12001 $aDai numeri la verità$enuovi documenti sulla famiglia, i palazzi e la cappella Sansevero 998 \\$1001SOBE00050413$12001 $aIn casa del principe di Sansevero$earchitettura, invenzioni, inventari 998 \\$1001SOBE00050414$12001 $aSupplica a Benedetto 14. LEADER 05267nam 2200649 a 450 001 9910144576903321 005 20170815122410.0 010 $a1-281-00216-X 010 $a9786611002169 010 $a0-470-12521-7 010 $a0-470-12520-9 035 $a(CKB)1000000000376972 035 $a(EBL)315213 035 $a(OCoLC)180191752 035 $a(SSID)ssj0000227399 035 $a(PQKBManifestationID)11175697 035 $a(PQKBTitleCode)TC0000227399 035 $a(PQKBWorkID)10264309 035 $a(PQKB)11537372 035 $a(MiAaPQ)EBC315213 035 $a(EXLCZ)991000000000376972 100 $a20061004d2007 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aPrinciples of modern digital design$b[electronic resource] /$fParag K. Lala 210 $aHoboken, N.J. $cWiley-Interscience$dc2007 215 $a1 online resource (437 p.) 300 $aDescription based upon print version of record. 311 $a0-470-07296-2 320 $aIncludes bibliographical references and index. 327 $aPRINCIPLES OF MODERN DIGITAL DESIGN; CONTENTS; Preface; 1 Number Systems and Binary Codes; 1.1 Introduction; 1.2 Decimal Numbers; 1.3 Binary Numbers; 1.3.1 Basic Binary Arithmetic; 1.4 Octal Numbers; 1.5 Hexadecimal Numbers; 1.6 Signed Numbers; 1.6.1 Diminished Radix Complement; 1.6.2 Radix Complement; 1.7 Floating-Point Numbers; 1.8 Binary Encoding; 1.8.1 Weighted Codes; 1.8.2 Nonweighted Codes; Exercises; 2 Fundamental Concepts of Digital Logic; 2.1 Introduction; 2.2 Sets; 2.3 Relations; 2.4 Partitions; 2.5 Graphs; 2.6 Boolean Algebra; 2.7 Boolean Functions 327 $a2.8 Derivation and Classification of Boolean Functions2.9 Canonical Forms of Boolean Functions; 2.10 Logic Gates; Exercises; 3 Combinational Logic Design; 3.1 Introduction; 3.2 Minimization of Boolean Expressions; 3.3 Karnaugh Maps; 3.3.1 Don't Care Conditions; 3.3.2 The Complementary Approach; 3.4 Quine-MCCluskey Method; 3.4.1 Simplification of Boolean Function with Don't Cares; 3.5 Cubical Representation of Boolean Functions; 3.5.1 Tautology; 3.5.2 Complementation Using Shannon's Expansion; 3.6 Heuristic Minimization of Logic Circuits; 3.6.1 Expand; 3.6.2 Reduce; 3.6.3 Irredundant 327 $a3.6.4 Espresso3.7 Minimization of Multiple-Output Functions; 3.8 NAND-NAND and NOR-NOR Logic; 3.8.1 NAND-NAND Logic; 3.8.2 NOR-NOR Logic; 3.9 Multilevel Logic Design; 3.9.1 Algebraic and Boolean Division; 3.9.2 Kernels; 3.10 Minimization of Multilevel Circuits Using Don't Cares; 3.10.1 Satisfiability Don't Cares; 3.10.2 Observability Don't Cares; 3.11 Combinational Logic Implementation Using EX-OR and AND Gates; 3.12 Logic Circuit Design Using Multiplexers and Decoders; 3.12.1 Multiplexers; 3.12.2 Demultiplexers and Decoders; 3.13 Arithmetic Circuits; 3.13.1 Half-Adders; 3.13.2 Full Adders 327 $a3.13.3 Carry-Lookahead Adders3.13.4 Carry-Select Adder; 3.13.5 Carry-Save Addition; 3.13.6 BCD Adders; 3.13.7 Half-Subtractors; 3.13.8 Full Subtractors; 3.13.9 Two's Complement Subtractors; 3.13.10 BCD Substractors; 3.13.11 Multiplication; 3.13.12 Comparator; 3.14 Combinational Circuit Design Using PLDs; 3.14.1 PROM; 3.14.2 PLA; 3.14.3 PAL; Exercises; References; 4 Fundamentals of Synchronous Sequential Circuits; 4.1 Introduction; 4.2 Synchronous and Asynchronous Operation; 4.3 Latches; 4.4 Flip-Flops; 4.4.1 D Flip-Flop; 4.4.2 JK Flip-Flop; 4.4.3 T Flip-Flop 327 $a4.5 Timing in Synchronous Sequential Circuits4.6 State Tables and State Diagrams; 4.7 Mealy and Moore Models; 4.8 Analysis of Synchronous Sequential Circuits; Exercises; References; 5 VHDL in Digital Design; 5.1 Introduction; 5.2 Entity and Architecture; 5.2.1 Entity; 5.2.2 Architecture; 5.3 Lexical Elements in VHDL; 5.4 Data Types; 5.5 Operators; 5.6 Concurrent and Sequential Statements; 5.7 Architecture Description; 5.8 Structural Description; 5.9 Behavioral Description; 5.10 RTL Description; Exercises; 6 Combinational Logic Design Using VHDL; 6.1 Introduction 327 $a6.2 Concurrent Assignment Statements 330 $aA major objective of this book is to fill the gap between traditional logic design principles and logic design/optimization techniques used in practice. Over the last two decades several techniques for computer-aided design and optimization of logic circuits have been developed. However, underlying theories of these techniques are inadequately covered or not covered at all in undergraduate text books. This book covers not only the ""classical"" material found in current text books but also selected materials that modern logic designers need to be familiar with. 606 $aLogic design 606 $aLogic circuits$xDesign and construction 606 $aDigital electronics 608 $aElectronic books. 615 0$aLogic design. 615 0$aLogic circuits$xDesign and construction. 615 0$aDigital electronics. 676 $a621.395 676 $a621.39732 700 $aLala$b Parag K.$f1948-$09381 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910144576903321 996 $aPrinciples of modern digital design$92239894 997 $aUNINA