LEADER 06136nam 22008175 450 001 9910143616503321 005 20251116234058.0 010 $a3-540-45352-0 024 7 $a10.1007/3-540-45352-0 035 $a(CKB)1000000000211327 035 $a(SSID)ssj0000323240 035 $a(PQKBManifestationID)11223086 035 $a(PQKBTitleCode)TC0000323240 035 $a(PQKBWorkID)10312546 035 $a(PQKB)10717802 035 $a(DE-He213)978-3-540-45352-9 035 $a(MiAaPQ)EBC3072071 035 $a(PPN)155203673 035 $a(BIP)6779372 035 $a(EXLCZ)991000000000211327 100 $a20121227d2000 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aFormal Techniques in Real-Time and Fault-Tolerant Systems $e6th International Symposium, FTRTFT 2000 Pune, India, September 20-22, 2000 Proceedings /$fedited by Mathai Joseph 205 $a1st ed. 2000. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2000. 215 $a1 online resource (X, 314 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v1926 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a3-540-41055-4 320 $aIncludes bibliographical references and index. 327 $aInvited Lectures -- Stability of Discrete Sampled Systems -- Issues in the Refinement of Distributed Programs -- Challenges in the Verification of Electronic Control Units -- Model Checking -- Scaling up Uppaal -- Decidable Model Checking of Probabilistic Hybrid Automata -- Fault Tolerance -- Invariant-Based Synthesis of Fault-Tolerant Systems -- Modeling Faults of Distributed, Reactive Systems -- Threshold and Bounded-Delay Voting in Critical Control Systems -- Automating the Addition of Fault-Tolerance -- Reliability Modelling of Time-Critical Distributed Systems -- Scheduling -- A Methodology for the Construction of Scheduled Systems -- A Dual Interpretation of ?Standard Constraints? in Parametric Scheduling -- Validation -- Co-Simulation of Hybrid Systems: Signal-Simulink -- A System for Object Code Validation -- Refinement -- Real-Time Program Refinement Using Auxiliary Variables -- On Refinement and Temporal Annotations -- Generalizing Action Systems to Hybrid Systems -- Verification -- Compositional Verification of Synchronous Networks -- Modelling Coordinated Atomic Actions in Timed CSP -- Logic and Automata -- A Logical Characterisation of Event Recording Automata -- Using Cylindrical Algebraic Decomposition for the Analysis of Slope Parametric Hybrid Automata -- Probabilistic Neighbourhood Logic -- An On-the-Fly Tableau Construction for a Real-Time Temporal Logic -- Verifying Universal Properties of Parameterized Networks. 330 $aThe six Schools and Symposia on Formal Techniques in Real Time and Fault Tolerant Systems (FTRTFT) have seen the eld develop from tentative explo- tions to a far higher degree of maturity, and from being under the scrutiny of a few interested software designers and academics to becoming a well-established area of inquiry. A number of new topics, such as hybrid systems, have been g- minated at these meetings and cross-links explored with related subjects such as scheduling theory. There has certainly been progress during these 12 years, but it is sobering to see how far and how fast practice has moved ahead in the same time, and how much more work remains to be done before the design of a mission-critical system can be based entirely on sound engineering principles underpinned by solid scienti c theory. The Sixth School and Symposium were organized by the Tata Research - velopment and Design Centre in Pune, India. The lectures at the School were given by Ian Hayes (U. of Queensland), Paritosh Pandya (Tata Institute of F- damental Research), Willem-Paul de Roever (Christian Albrechts U. ) and Joseph Sifakis (VERIMAG). There were three invited lectures at the Symposium, by Werner Damm (U. of Oldenburg), Nicholas Halbwachs (VERIMAG) and Yoram Moses (Technion). A sizable number of submissions were received for the Symposium from a- hors representing 16 di erent countries. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v1926 606 $aProgramming languages (Electronic computers) 606 $aComputer architecture 606 $aComputer logic 606 $aMicroprocessors 606 $aComputers, Special purpose 606 $aLogic design 606 $aProgramming Languages, Compilers, Interpreters$3https://scigraph.springernature.com/ontologies/product-market-codes/I14037 606 $aComputer System Implementation$3https://scigraph.springernature.com/ontologies/product-market-codes/I13057 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aSpecial Purpose and Application-Based Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I13030 606 $aLogic Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I12050 615 0$aProgramming languages (Electronic computers) 615 0$aComputer architecture. 615 0$aComputer logic. 615 0$aMicroprocessors. 615 0$aComputers, Special purpose. 615 0$aLogic design. 615 14$aProgramming Languages, Compilers, Interpreters. 615 24$aComputer System Implementation. 615 24$aLogics and Meanings of Programs. 615 24$aProcessor Architectures. 615 24$aSpecial Purpose and Application-Based Systems. 615 24$aLogic Design. 676 $a004/.33 702 $aJoseph$b Mathai$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aFTRTFT 2000 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910143616503321 996 $aFormal Techniques in Real-Time and Fault-Tolerant Systems$91944996 997 $aUNINA