LEADER 05912nam 22008175 450 001 9910143594003321 005 20200706092202.0 010 $a3-540-44570-6 024 7 $a10.1007/3-540-44570-6 035 $a(CKB)1000000000211516 035 $a(SSID)ssj0000324088 035 $a(PQKBManifestationID)11282874 035 $a(PQKBTitleCode)TC0000324088 035 $a(PQKBWorkID)10304853 035 $a(PQKB)11453536 035 $a(DE-He213)978-3-540-44570-8 035 $a(MiAaPQ)EBC3072898 035 $a(PPN)155203819 035 $a(EXLCZ)991000000000211516 100 $a20121227d2001 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntelligent Memory Systems $eSecond International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers /$fedited by Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin 205 $a1st ed. 2001. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2001. 215 $a1 online resource (VIII, 200 p.) 225 1 $aLecture Notes in Computer Science,$x0302-9743 ;$v2107 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-42328-1 327 $aMemory Technology -- A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro -- Software Controlled Reconfigurable On-chip Memory for High Performance Computing -- Processor and Memory Architecture -- Content-Based Prefetching: Initial Results -- Memory System Support for Dynamic Cache Line Assembly -- Adaptively Mapping Code in an Intelligent Memory Architecture -- Applications and Operating Systems -- The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems? -- Memory Management in a PIM-Based Architecture -- Compiler Technology -- Exploiting On-chip Memory Bandwidth in the VIRAM Compiler -- FlexCache: A Framework for Flexible Compiler Generated Data Caching -- Poster Session -- Aggressive Memory-Aware Compilation -- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips? -- SAGE: A New Analysis and Optimization System for FlexRAM Architecture -- Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems -- The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems -- Compiler-Directed Cache Line Size Adaptivity ? -- Summary of Question/Answer Sessions for Workshop Presentations. 330 $aWe are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology. 410 0$aLecture Notes in Computer Science,$x0302-9743 ;$v2107 606 $aArtificial intelligence 606 $aComputer engineering 606 $aComputer memory systems 606 $aComputer organization 606 $aOperating systems (Computers) 606 $aComputer logic 606 $aArtificial Intelligence$3https://scigraph.springernature.com/ontologies/product-market-codes/I21000 606 $aComputer Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I27000 606 $aMemory Structures$3https://scigraph.springernature.com/ontologies/product-market-codes/I12034 606 $aComputer Systems Organization and Communication Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/I13006 606 $aOperating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14045 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 615 0$aArtificial intelligence. 615 0$aComputer engineering. 615 0$aComputer memory systems. 615 0$aComputer organization. 615 0$aOperating systems (Computers). 615 0$aComputer logic. 615 14$aArtificial Intelligence. 615 24$aComputer Engineering. 615 24$aMemory Structures. 615 24$aComputer Systems Organization and Communication Networks. 615 24$aOperating Systems. 615 24$aLogics and Meanings of Programs. 676 $a005.4/35 702 $aChong$b Frederic T$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aKozyrakis$b Christoforos$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aOskin$b Mark$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aIMS 2000 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910143594003321 996 $aIntelligent Memory Systems$92257106 997 $aUNINA