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100   $a20160829d2005      uy 
101 0 $aeng
135   $aur|||||||||||
181   $ctxt
182   $cc
183   $acr
200 10$aDFT 2005: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (03-05 October 2005/Monterey, CA)
210 31$a[Place of publication not identified]$cIEEE Computer Society Press$d2005
215   $a1 online resource (xii, 602 pages) $cillustrations
300   $aBibliographic Level Mode of Issuance: Monograph
311 08$a9780769524641 
311 08$a0769524648 
330   $aAnnotation DFT 2005 showcases the latest research results on yield analysis and modeling, scan design and test data compression, reconfiguration, error correcting codes and circuits, and fault detection and tolerance for sensor and flash memory. Its also covers delay fault test and timing consideration, interconnect test, approaches for soft error, on-line and concurrent fault detection, fault and error tolerant systems, and test scheduling and software-based test.
606   $aFault-tolerant computing$vCongresses
615  0$aFault-tolerant computing
676   $a004.2
700   $aAitken$b Robert$0282271
801  0$bPQKB
906   $aPROCEEDING
912   $a9910142311703321
996   $aDFT 2005: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (03-05 October 2005$94434175
997   $aUNINA