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100   $a20160829d1999      uy              
101 0 $aeng
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181   $ctxt
182   $cc
183   $acr
200 00$a1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System
210 31$a[Place of publication not identified]$cIEEE$d1999
215   $a1 online resource (viii, 390 pages) $cillustrations
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a0-7381-1771-4 
330   $aWays for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.
606   $aIntegrated circuits
606   $aMicroelectronics
615  0$aIntegrated circuits.
615  0$aMicroelectronics.
676   $a621.3815
801  0$bPQKB
906   $aDOCUMENT
912   $a9910142053503321
996   $a1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System$92575184
997   $aUNINA