LEADER 01312nam1 22002893i 450 001 SUN0093695 005 20130531101644.797 100 $a20130517g18701874 |0frec50 ba 101 $afre 102 $aBE 105 $a|||| ||||| 200 1 $aCours de droit romain precede d'une introduction contenant l'histoire de la legislation romaine$fCharles Maynz 205 $a3. ed 210 $aBruxelles$cPolytecnique$aParis$cDurand-Pedone$d1870-1874 215 $a3 vol.$d25 cm. 463 \1$1001SUN0093698$12001 $a<<>>Cours de droit romain precede d'une introduction contenant l'histoire de la legislation romaine 1 463 \1$1001SUN0093703$12001 $a<<>>Cours de droit romain precede d'une introduction contenant l'histoire de la legislation romaine 2 463 \1$1001SUN0093704$12001 $a<<>>Cours de droit romain precede d'une introduction contenant l'histoire de la legislation romaine 3 620 $dParis$3SUNL000046 620 $dBruxelles$3SUNL000216 700 1$aMaynz$b, Charles$3SUNV075180$0236241 712 $aPolytecnique$3SUNV009289$4650 712 $aDurand-Pedone$3SUNV009290$4650 801 $aIT$bSOL$c20181109$gRICA 912 $aSUN0093695 996 $aCours de droit romain precede d'une introduction contenant l'histoire de la legislation romaine$91407839 997 $aUNICAMPANIA LEADER 01594nam 2200361Ia 450 001 996395068603316 005 20210104171611.0 035 $a(CKB)3810000000016466 035 $a(EEBO)2240901206 035 $a(OCoLC)ocn489265223e 035 $a(OCoLC)489265223 035 $a(EXLCZ)993810000000016466 100 $a20091216d1699 uy 0 101 0 $aeng 135 $aurbn||||a|bb| 200 10$aTo His Excellency Richard Earl of Bellomont, capt. general and governour in chief of His Majesties province of New-York, &c$b[electronic resource] $ethe humble petition and remonstrance of the representatives of this His Majesties province of New-York in America, convened in General Assembly 210 $a[New York $cWilliam Bradford$d1699] 215 $a3 p 300 $aCaption title. 300 $aSigned and dated at end: "Die Lunae 15 May 1699. Abraha. Gouverneur, speaker." 300 $aImprint of publication suggested by Wing (2nd ed.). 300 $aReproduction of original in: New York Public Library. 330 $aeebo-0103 607 $aNew York (State)$xPolitics and government$yTo 1775$vEarly works to 1800 608 $aBroadsides$zNew York$y17th century.$2rbgenr 701 $aBellomont$b Richard Coote$cEarl of,$f1636-1701.$01015328 712 02$aNew York (Colony).$bGovernor (1698-1701 : Bellomont) 801 0$bUMI 801 1$bUMI 906 $aBOOK 912 $a996395068603316 996 $aTo His Excellency Richard Earl of Bellomont, capt. general and governour in chief of His Majesties province of New-York, &c$92387591 997 $aUNISA LEADER 05768nam 2200745Ia 450 001 9910141240503321 005 20200520144314.0 010 $a1-283-28288-7 010 $a9786613282880 010 $a1-118-14653-0 010 $a1-118-14652-2 010 $a1-118-14650-6 035 $a(CKB)2670000000128082 035 $a(EBL)817361 035 $a(OCoLC)757486963 035 $a(SSID)ssj0000554671 035 $a(PQKBManifestationID)11308402 035 $a(PQKBTitleCode)TC0000554671 035 $a(PQKBWorkID)10516823 035 $a(PQKB)10946358 035 $a(MiAaPQ)EBC817361 035 $a(Au-PeEL)EBL817361 035 $a(CaPaEBR)ebr10560671 035 $a(CaONFJC)MIL328288 035 $a(PPN)179237667 035 $a(EXLCZ)992670000000128082 100 $a20110527d2011 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aEmbedded SOPC design with NIOS II processor and VHDL examples$b[electronic resource] /$fPong P. Chu 210 $aHoboken, N.J. $cWiley$dc2011 215 $a1 online resource (738 p.) 300 $aDescription based upon print version of record. 311 $a1-118-00888-X 320 $aIncludes bibliographical references and index. 327 $aEmbedded SOPC Design with Nios II Processor and VHDL Examples; CONTENTS; Preface; Acknowledgments; 1 Overview of Embedded System; 1.1 Introduction; 1.1.1 Definition of an embedded system; 1.1.2 Example systems; 1.2 System design requirements; 1.3 Embedded SoPC systems; 1.3.1 Basic development flow; 1.4 Book organization; 1.5 Bibliographic notes; PART I BASIC DIGITAL CIRCUITS DEVELOPMENT; 2 Gate-level Combinational Circuit; 2.1 Overview of VHDL; 2.2 General description; 2.2.1 Basic lexical rules; 2.2.2 Library and package; 2.2.3 Entity declaration; 2.2.4 Data type and operators 327 $a2.2.5 Architecture body2.2.6 Code of a 2-bit comparator; 2.3 Structural description; 2.4 Testbench; 2.5 Bibliographic notes; 2.6 Suggested experiments; 2.6.1 Code for gate-level greater-than circuit; 2.6.2 Code for gate-level binary decoder; 3 Overview of FPGA and EDA Software; 3.1 FPGA; 3.1.1 Overview of a general FPGA device; 3.1.2 Overview of the Altera Cyclone II devices; 3.2 Overview of the Altera DE1 and DE2 boards; 3.3 Development flow; 3.4 Overview of Quartus II; 3.5 Short tutorial of Quartus II; 3.5.1 Create the design project; 3.5.2 Create a testbench and perform the RTL simulation 327 $a3.5.3 Compile the project3.5.4 Perform timing analysis; 3.5.5 Program the FPGA device; 3.6 Short tutorial on the ModelSim HDL simulator; 3.7 Bibliographic notes; 3.8 Suggested experiments; 3.8.1 Gate-level greater-than circuit; 3.8.2 Gate-level binary decoder; 4 RT-level Combinational Circuit; 4.1 RT-level components; 4.1.1 Relational operators; 4.1.2 Arithmetic operators; 4.1.3 Other synthesis-related VHDL constructs; 4.1.4 Summary; 4.2 Routing circuit with concurrent assignment statements; 4.2.1 Conditional signal assignment statement; 4.2.2 Selected signal assignment statement 327 $a4.3 Modeling with a process4.3.1 Process; 4.3.2 Sequential signal assignment statement; 4.4 Routing circuit with if and case statements; 4.4.1 If statement; 4.4.2 Case statement; 4.4.3 Comparison to concurrent statements; 4.4.4 Unintended memory; 4.5 Constants and generics; 4.5.1 Constants; 4.5.2 Generics; 4.6 Design examples; 4.6.1 Hexadecimal digit to seven-segment LED decoder; 4.6.2 Sign-magnitude adder; 4.6.3 Barrel shifter; 4.6.4 Simplified floating-point adder; 4.7 Bibliographic notes; 4.8 Suggested experiments; 4.8.1 Multi-function barrel shifter; 4.8.2 Dual-priority encoder 327 $a4.8.3 BCD incrementor4.8.4 Floating-point greater-than circuit; 4.8.5 Floating-point and signed integer conversion circuit; 4.8.6 Enhanced floating-point adder; 5 Regular Sequential Circuit; 5.1 Introduction; 5.1.1 D FF and register; 5.1.2 Synchronous system; 5.1.3 Code development; 5.2 HDL code of the basic storage elements; 5.2.1 D FF; 5.2.2 Register; 5.2.3 Register file; 5.2.4 SRAM; 5.3 Simple design examples; 5.3.1 Shift register; 5.3.2 Binary counter and variant; 5.4 Testbench for sequential circuits; 5.5 Timing analysis; 5.5.1 Timing parameters; 5.5.2 Timing considerations in Quartus II 327 $a5.6 Case study 330 $aThe book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelb 606 $aSystems on a chip 606 $aField programmable gate arrays 606 $aComputer input-output equipment$xDesign and construction 606 $aVHDL (Computer hardware description language) 615 0$aSystems on a chip. 615 0$aField programmable gate arrays. 615 0$aComputer input-output equipment$xDesign and construction. 615 0$aVHDL (Computer hardware description language) 676 $a621.392 676 $a621.392 676 $a621.395 686 $aTEC008010$2bisacsh 700 $aChu$b Pong P.$f1959-$0521922 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910141240503321 996 $aEmbedded SOPC design with NIOS II processor and VHDL examples$91969905 997 $aUNINA