LEADER 02530oam 2200433zu 450 001 9910141193903321 005 20241212220149.0 035 $a(CKB)2670000000140190 035 $a(SSID)ssj0000669468 035 $a(PQKBManifestationID)12241792 035 $a(PQKBTitleCode)TC0000669468 035 $a(PQKBWorkID)10709652 035 $a(PQKB)10157802 035 $a(NjHacI)992670000000140190 035 $a(EXLCZ)992670000000140190 100 $a20160829d2011 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$a2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming 210 31$a[Place of publication not identified]$cIEEE$d2011 215 $a1 online resource (xvii, 359 pages) 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9780769545752 311 08$a0769545750 311 08$a9781457718083 311 08$a1457718081 330 $aIn the recent years, embedded systems began to be used in sensitive applications such as personal digital assistants and smart cards. Due to very strict cost and power constrains, the support for cryptography provided by these devices is often limited to either public or private key primitives. This limitation is much more evident in devices where the cryptographic algorithms are implemented using hardware resources. In this paper, we propose an extension of a public-key cryptosystem to support also private-key, and we evaluate our architecture on FPGA platforms. In particular, we propose a new arithmetic unit in which the polynomial modular multiplication of ECC is extended to compute also the polynomial arithmetic operations over binary extended field of AES. We compare our design with an architecture obtained by instantiating state of the art implementation of AES and ECC and we evaluate the trade-offs. The experimental results show that our proposed architecture takes up less hardware resources. Nevertheless, the achieved performances are better compared to the ECC reference core, while the ones compared to AES only implementation are comparable with the state of the art. 606 $aHigh performance computing$vCongresses 615 0$aHigh performance computing 676 $a004.11 702 $aIEEE Staff 801 0$bPQKB 906 $aPROCEEDING 912 $a9910141193903321 996 $a2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming$92401130 997 $aUNINA