LEADER 05925nam 2200745 450 001 9910140576503321 005 20221206180221.0 010 $a1-282-68797-2 010 $a9786612687976 010 $a0-470-82379-8 010 $a0-470-82378-X 024 7 $a10.1002/9780470823798 035 $a(CKB)2670000000018833 035 $a(EBL)529950 035 $a(SSID)ssj0000423303 035 $a(PQKBManifestationID)11280071 035 $a(PQKBTitleCode)TC0000423303 035 $a(PQKBWorkID)10438771 035 $a(PQKB)10003507 035 $a(CaBNVSL)mat05676102 035 $a(IDAMS)0b0000648144b7d1 035 $a(IEEE)5676102 035 $a(Au-PeEL)EBL529950 035 $a(CaPaEBR)ebr10387091 035 $a(CaONFJC)MIL268797 035 $a(OCoLC)632158145 035 $a(CaSebORM)9780470823774 035 $a(MiAaPQ)EBC529950 035 $a(PPN)263010015 035 $a(EXLCZ)992670000000018833 100 $a20151221d2010 uy 101 0 $aeng 135 $aurunu||||| 181 $ctxt 182 $cc 183 $acr 200 00$aMobile 3D graphics SoC $efrom algorithm to chip /$fJeong-Ho Woo ... [et al.] 205 $a1st edition 210 1$aSingapore ;$cJohn Wiley & Sons,$dc2010. 210 2$a[Piscataqay, New Jersey] :$cIEEE Xplore,$d[2010] 215 $a1 online resource (342 p.) 300 $aIncludes index. 311 $a0-470-82377-1 320 $aIncludes bibliographical references and index. 327 $aPreface -- 1 Introduction -- 1.1 Mobile 3D Graphics -- 1.2 Mobile Devices and Design Challenges -- 1.2.1 Mobile Computing Power -- 1.2.2 Mobile Display Devices -- 1.2.3 Design Challenges -- 1.3 Introduction to SoC Design -- 1.4 About this Book -- 2 Application Platform -- 2.1 SoC Design Paradigms -- 2.1.1 Platform and Set-based Design -- 2.1.2 Modeling: Memory and Operations -- 2.2 System Architecture -- 2.2.1 Reference Machine and API -- 2.2.2 Communication Architecture Design -- 2.2.3 System Analysis -- 2.3 Low-power SoC Design -- 2.3.1 CMOS Circuit-level Low-power Design -- 2.3.2 Architecture-level Low-power Design -- 2.3.3 System-level Low-power Design -- 2.4 Network-on-Chip based SoC -- 2.4.1 Network-on-Chip Basics -- 2.4.2 NoC Design Considerations -- 2.4.3 Case Studies of Chip Implementation -- 3 Introduction to 3D Graphics -- 3.1 The 3D Graphics Pipeline -- 3.1.1 The Application Stage -- 3.1.2 The Geometry Stage -- 3.1.3 The Rendering Stage -- 3.2 Programmable 3D Graphics -- 3.2.1 Programmable Graphics Pipeline -- 3.2.2 Shader Models -- 4 Mobile 3D Graphics -- 4.1 Principles of Mobile 3D Graphics -- 4.1.1 Application Challenges -- 4.1.2 Design Principles -- 4.2 Mobile 3D Graphics APIs -- 4.2.1 KAIST MobileGL -- 4.2.2 Khronos OpenGL-ES -- 4.2.3 Microsoft's Direct3D-Mobile -- 4.3 Summary and Future Directions -- 5 Mobile 3D Graphics SoC -- 5.1 Low-power Rendering Processor -- 5.1.1 Early Depth Test -- 5.1.2 Logarithmic Datapaths -- 5.1.3 Low-power Texture Unit -- 5.1.4 Tile-based Rendering -- 5.1.5 Texture Compression -- 5.1.6 Texture Filtering and Anti-aliasing -- 5.2 Low-power Shader -- 5.2.1 Vertex Cache -- 5.2.2 Low-power Register File -- 5.2.3 Mobile Unified Shader -- 6 Real Chip Implementations -- 6.1 KAIST RAMP Architecture -- 6.1.1 RAMP-IV -- 6.1.2 RAMP-V -- 6.1.3 RAMP-VI -- 6.1.4 RAMP-VII -- 6.2 Industry Architecture -- 6.2.1 nVidia Mobile GPU - SC10 and Tegra -- 6.2.2 Sony PSP -- 6.2.3 Imagination Technology MBX/SGX -- 7 Low-power Rasterizer Design. 327 $a7.1 Target System Architecture -- 7.2 Summary of Performance and Features -- 7.3 Block Diagram of the Rasterizer -- 7.4 Instruction Set Architecture (ISA) -- 7.5 Detailed Design with Register Transfer Level Code -- 7.5.1 Rasterization Top Block -- 7.5.2 Pipeline Architecture -- 7.5.3 Main Controller Design -- 7.5.4 Rasterization Core Unit -- 8 The Future of Mobile 3D Graphics -- 8.1 Game and Mapping Applications Involving Networking -- 8.2 Moves Towards More User-centered Applications -- 8.3 Final Remarks -- Appendix Verilog HDL Design -- A.1 Introduction to Verilog Design -- A.2 Design Level -- A.2.1 Behavior Level -- A.2.2 Register Transfer Level -- A.2.3 Gate Level -- A.3 Design Flow -- A.3.1 Specification -- A.3.2 High-level Design -- A.3.3 Low-level Design -- A.3.4 RTL Coding -- A.3.5 Simulation -- A.3.6 Synthesis -- A.3.7 Placement and Routing -- A.4 Verilog Syntax -- A.4.1 Modules -- A.4.2 Logic Values and Numbers -- A.4.3 Data Types -- A.4.4 Operators -- A.4.5 Assignment -- A.4.6 Ports and Connections -- A.4.7 Expressions -- A.4.8 Instantiation -- A.4.9 Miscellaneous -- A.5 Example of Four-bit Adder with Zero Detection -- A.6 Synthesis Scripts -- Glossaries -- Index. 330 $aThe first book to explain the principals behind mobile 3D hardware implementation, helping readers understand advanced algorithms, produce low-cost, low-power SoCs, or become familiar with embedded systems As mobile broadcasting and entertainment applications evolve, there is increasing interest in 3D graphics within the field of mobile electronics, particularly for handheld devices. In Mobile 3D Graphics SoC, Yoo provides a comprehensive understanding of the algorithms of mobile 3D graphics and their real chip implementation methods. 3D graphics SoC (System on a Chip) architect 517 3 $aMobile three-dimensional graphics systems on a chip 606 $aComputer graphics 606 $aMobile computing 606 $aSystems on a chip 606 $aThree-dimensional display systems 615 0$aComputer graphics. 615 0$aMobile computing. 615 0$aSystems on a chip. 615 0$aThree-dimensional display systems. 676 $a621.3815 701 $aWoo$b Jeong-Ho$0845735 801 0$bCaBNVSL 801 1$bCaBNVSL 801 2$bCaBNVSL 906 $aBOOK 912 $a9910140576503321 996 $aMobile 3D graphics SoC$91888027 997 $aUNINA