LEADER 03691nam 2200673 450 001 9910139930203321 005 20221206174919.0 010 $a1-282-38218-7 010 $a9786612382185 010 $a0-470-82409-3 010 $a0-470-82408-5 024 7 $a10.1002/9780470824092 035 $a(CKB)1000000000799847 035 $a(EBL)479860 035 $a(SSID)ssj0000366925 035 $a(PQKBManifestationID)11275066 035 $a(PQKBTitleCode)TC0000366925 035 $a(PQKBWorkID)10418689 035 $a(PQKB)11324759 035 $a(MiAaPQ)EBC479860 035 $a(CaBNVSL)mat05453758 035 $a(IDAMS)0b00006481237fee 035 $a(IEEE)5453758 035 $a(Au-PeEL)EBL479860 035 $a(CaPaEBR)ebr10325826 035 $a(CaONFJC)MIL238218 035 $a(OCoLC)669008259 035 $a(PPN)254409873 035 $a(EXLCZ)991000000000799847 100 $a20151221d2010 uy 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aTransient-induced latchup in CMOS integrated circuits /$fMing-Dou Ker and Sheng-Fu Hsu 210 1$aSingapore ;$cWiley,$dc2009. 210 2$a[Piscataqay, New Jersey] :$cIEEE Xplore,$d[2010] 215 $a1 online resource (265 p.) 300 $aDescription based upon print version of record. 311 $a0-470-82407-7 320 $aIncludes bibliographical references and index. 327 $aPhysical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process. 330 $a"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description. 606 $aMetal oxide semiconductors, Complementary$xDefects 606 $aMetal oxide semiconductors, Complementary$xReliability 615 0$aMetal oxide semiconductors, Complementary$xDefects. 615 0$aMetal oxide semiconductors, Complementary$xReliability. 676 $a621.3815 676 $a621.39/5 700 $aKer$b Ming-Dou$0845643 701 $aHsu$b Sheng-Fu$0845644 801 0$bCaBNVSL 801 1$bCaBNVSL 801 2$bCaBNVSL 906 $aBOOK 912 $a9910139930203321 996 $aTransient-induced latchup in CMOS integrated circuits$91887816 997 $aUNINA