LEADER 02716oam 2200433zu 450 001 9910139196303321 005 20241212215855.0 010 $a9780769543062 010 $a0769543065 035 $a(CKB)2560000000059173 035 $a(SSID)ssj0000527790 035 $a(PQKBManifestationID)12178393 035 $a(PQKBTitleCode)TC0000527790 035 $a(PQKBWorkID)10544620 035 $a(PQKB)10912076 035 $a(NjHacI)992560000000059173 035 $a(EXLCZ)992560000000059173 100 $a20160829d2011 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$a2011 IEEE 6th International Workshop on Electronic Design, Test and Application 210 31$a[Place of publication not identified]$cI E E E$d2011 215 $a1 online resource (xiv, 290 pages) $cillustrations 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9781424493579 311 08$a1424493579 330 $aDesigning aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper develops an approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input OR/NOR logic. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the importance of the technique from the viewpoint simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments. 606 $aElectronics$xDesign$vCongresses 615 0$aElectronics$xDesign 676 $a621.381 702 $aIEEE Staff 801 0$bPQKB 906 $aPROCEEDING 912 $a9910139196303321 996 $a2011 IEEE 6th International Workshop on Electronic Design, Test and Application$92361683 997 $aUNINA