LEADER 00953nam--2200337---450- 001 990001876960203316 005 20050930132629.0 035 $a000187696 035 $aUSA01000187696 035 $a(ALEPH)000187696USA01 035 $a000187696 100 $a20040727d1954----km-y0itay0103----ba 101 0 $aita 102 $aIT 105 $a||||||||001yy 200 1 $aRaffaello Lambruschini$eil pensiero pedagogico$fFrancesco Rinaldi 210 $aRovigo$cIstituto Padano di Arti Grafiche$d1954 215 $a204 p.$d19 cm 410 0$12001 454 1$12001 461 1$1001-------$12001 700 1$aRINALDI,$bFrancesco$0548501 801 0$aIT$bsalbc$gISBD 912 $a990001876960203316 951 $aII.4. 2313(VI C 1097)$b11099 L.M.$cVI C 959 $aBK 969 $aUMA 979 $aSIAV3$b10$c20040727$lUSA01$h0906 979 $aCOPAT3$b90$c20050930$lUSA01$h1326 996 $aRaffaello Lambruschini$9955131 997 $aUNISA LEADER 03281oam 2200433zu 450 001 9910139122103321 005 20241212215902.0 010 $a9781424460243 010 $a1424460247 035 $a(CKB)2560000000009641 035 $a(SSID)ssj0000452603 035 $a(PQKBManifestationID)12194515 035 $a(PQKBTitleCode)TC0000452603 035 $a(PQKBWorkID)10468521 035 $a(PQKB)11748079 035 $a(NjHacI)992560000000009641 035 $a(EXLCZ)992560000000009641 100 $a20160829d2010 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$a2010 IEEE International Symposium on Performance Analysis of Systems and Software 210 31$a[Place of publication not identified]$cIEEE$d2010 215 $a1 online resource (ix, 248 pages) $cillustrations 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9781424460236 311 08$a1424460239 330 $aAs processor performance continues to outgrow memory capacity and bandwidth, system and application performance has become constrained by the memory subsystem. Promising new technologies like Phase Change Memory (PCM) and Flash have emerged which may add capacity at a cost cheaper than conventional DRAM, but at the cost of added latency and poor endurance. It is likely that systems leveraging these new memory technologies in the memory subsystem would require an innovative memory system architecture to gain the benefit of added capacity while mitigating the costs of latency and potential device wear-out. One such proposed architecture is a hierarchical memory sub-system with a faster but costly memory (e.g., DRAM) acting as a cache for a slower but cheaper memory e.g., solid state memory like NAND flash, NOR flash or PCM. The memory subsystem is now a hybrid of two different memory technologies, exploiting the cost effectiveness and non-volatility of solid state memory devices with the speed of traditional DRAM. In order to study the performance tradeoffs with such hierarchical architectures one needs to first study the effect of having a last level cache, which is much larger than the caches in existing systems. Existing tools and methodologies for cache evaluation fall short. We develop a multi-processor system prototype that runs applications with a coherently-attached FPGA which can emulate different memory architectures for long periods of time. The output of the system is not a memory trace, but the performance results of the emulated memory system design which may be used at any time to evaluate the design tradeoffs. The large cache will filter out references going to the solid state memory. Thus the miss ratio of the large cache is an important metric. The sensitivity of the miss ratio to configuration parameters like cache size and line size needs to be evaluated to identify the right set of parameters. 606 $aComputer systems$xEvaluation$vCongresses 615 0$aComputer systems$xEvaluation 676 $a004.24 702 $aIEEE Staff 801 0$bPQKB 906 $aPROCEEDING 912 $a9910139122103321 996 $a2010 IEEE International Symposium on Performance Analysis of Systems and Software$92531614 997 $aUNINA