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010   $a0-7381-4694-3
024 7 $a10.1109/IEEESTD.2005.96465
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101 0 $aeng
135   $aur|||||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aIEEE Std 1500-2005 $eIEEE Standard Testability Method for Embedded Core-based Integrated Circuits /$fInstitute of Electrical and Electronics Engineers
210  1$aNew York, NY :$cIEEE,$d2005.
215   $a1 online resource (viii, 117 pages) $cillustrations (some color)
330   $aThis standard defines a mechanism for the test of core designs within a system on chip (SoC). This mechanism constitutes a hardware architecture and leverages the core test language (CTL) to facilitate communication between core designers and core integrators.
517   $aIEEE Std 1500-2005
606   $aEmbedded computer systems
606   $aIntegrated circuits$xTesting
606   $aSystems on a chip
615  0$aEmbedded computer systems.
615  0$aIntegrated circuits$xTesting.
615  0$aSystems on a chip.
676   $a004.16
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906   $aDOCUMENT
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996   $aIEEE Std 1500-2005$93646594
997   $aUNINA