LEADER 05828nam 2200805 450 001 9910132172303321 005 20200520144314.0 010 $a1-118-70147-X 010 $a1-118-70140-2 010 $a1-118-70168-2 035 $a(CKB)3710000000214420 035 $a(EBL)1758401 035 $a(SSID)ssj0001288764 035 $a(PQKBManifestationID)12585293 035 $a(PQKBTitleCode)TC0001288764 035 $a(PQKBWorkID)11294771 035 $a(PQKB)11143763 035 $a(PQKBManifestationID)16045140 035 $a(PQKB)24499556 035 $a(OCoLC)891398198 035 $a(DLC) 2014021528 035 $a(Au-PeEL)EBL1758401 035 $a(CaPaEBR)ebr10909193 035 $a(CaONFJC)MIL633693 035 $a(OCoLC)886111716 035 $a(CaSebORM)9781119965183 035 $a(MiAaPQ)EBC1758401 035 $a(EXLCZ)993710000000214420 100 $a20140831h20152015 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$aESD $eanalog circuits and design /$fSteven H Voldman 205 $a1st edition 210 1$aChichester, England :$cWiley,$d2015. 210 4$dİ2015 215 $a1 online resource (292 p.) 225 1 $aESD Series 300 $aDescription based upon print version of record. 311 $a1-119-96518-7 320 $aIncludes bibliographical references at the end of each chapters and index. 327 $aESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress 327 $a1.7.1 Electrical Overcurrent 1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout 327 $a2.1 Analog Design Layout Revisited 2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout 327 $a2.6.4 Thermoelectric Cancellation Layout 2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror 327 $a3.7 Voltage Regulators 3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode 327 $a4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET 330 $aA comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres 410 0$aESD series. 606 $aSemiconductors$xProtection 606 $aAnalog integrated circuits$xProtection 606 $aAnalog integrated circuits$xDesign and construction 606 $aElectrostatics 606 $aStatic eliminators 615 0$aSemiconductors$xProtection. 615 0$aAnalog integrated circuits$xProtection. 615 0$aAnalog integrated circuits$xDesign and construction. 615 0$aElectrostatics. 615 0$aStatic eliminators. 676 $a621.3815/3 700 $aVoldman$b Steven H.$0872423 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910132172303321 996 $aESD$91958013 997 $aUNINA