LEADER 05423nam 2200649 450 001 9910131514203321 005 20170822132259.0 010 $a1-118-84112-3 010 $a1-118-84110-7 010 $a1-118-84111-5 035 $a(CKB)3710000000442590 035 $a(EBL)2075687 035 $a(SSID)ssj0001515180 035 $a(PQKBManifestationID)12525310 035 $a(PQKBTitleCode)TC0001515180 035 $a(PQKBWorkID)11498636 035 $a(PQKB)11443543 035 $a(PQKBManifestationID)16226318 035 $a(PQKB)21424555 035 $a(MiAaPQ)EBC4039159 035 $a(MiAaPQ)EBC2075687 035 $a(DLC) 2015024730 035 $a(PPN)194928144 035 $a(EXLCZ)993710000000442590 100 $a20150720h20152015 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aComputer principles and design in Verilog HDL /$fYamin Li, Hosei University 210 1$aSingapore :$cWiley :$cTsinghua University Press,$d2015. 210 4$dİ2015 215 $a1 online resource (1376 p.) 300 $aDescription based upon print version of record. 311 $a1-118-84109-3 320 $aIncludes bibliographical references and index. 327 $aCover; Table of Contents; Title Page; Copyright; List of Figures; List of Tables; Preface; Chapter 1: Computer Fundamentals and Performance Evaluation; 1.1 Overview of Computer Systems; 1.2 Basic Structure of Computers; 1.3 Improving Computer Performance; 1.4 Hardware Description Languages; Exercises; Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL; 2.1 Logic Gates; 2.2 Logic Circuit Design in Verilog HDL; 2.3 CMOS Logic Gates; 2.4 Four Levels/Styles of Verilog HDL; 2.5 Combinational Circuit Design; 2.6 Sequential Circuit Design; Exercises 327 $aChapter 3: Computer Arithmetic Algorithms and Implementations3.1 Binary Integers; 3.2 Binary Addition and Subtraction; 3.3 Binary Multiplication Algorithms; 3.4 Binary Division Algorithms; 3.5 Binary Square Root Algorithms; Exercises; Chapter 4: Instruction Set Architecture and ALU Design; 4.1 Instruction Set Architecture; 4.2 MIPS Instruction Format and Registers; 4.3 MIPS Instructions and AsmSim Tool; 4.4 ALU Design; Exercises; Chapter 5: Single-Cycle CPU Design in Verilog HDL; 5.1 The Circuits Required for Executing an Instruction; 5.2 Register File Design 327 $a5.3 Single-Cycle CPU Datapath Design5.4 Single-Cycle CPU Control Unit Design; 5.5 Test Program and Simulation Waveform; Exercises; Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL; 6.1 Exceptions and Interrupts; 6.2 Design of CPU with Exception and Interrupt Mechanism; 6.3 The CPU Exception and Interrupt Tests; Exercises; Chapter 7: Multiple-Cycle CPU Design in Verilog HDL; 7.1 Dividing Instruction Execution into Several Clock Cycles; 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes; 7.3 Multiple-Cycle CPU Control Unit Design; 7.4 Memory and Test Program 327 $aExercisesChapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL; 8.1 Pipelining; 8.2 Pipeline Hazards and Solutions; 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes; 8.4 Precise Interrupts/Exceptions in Pipelined CPU; 8.5 Design of Pipelined CPU with Precise Interrupt/Exception; Exercises; Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL; 9.1 IEEE 754 Floating-Point Data Formats; 9.2 Converting between Floating-Point Number and Integer; 9.3 Floating-Point Adder (FADD) Design; 9.4 Floating-Point Multiplier (FMUL) Design 327 $a9.5 Floating-Point Divider (FDIV) Design9.6 Floating-Point Square Root (FSQRT) Design; Exercises; Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL; 10.1 CPU/FPU Pipeline Model; 10.2 Design of Register File with Two Write Ports; 10.3 Data Dependency and Pipeline Stalls; 10.4 Pipelined CPU/FPU Design in Verilog HDL; 10.5 Memory Modules and Pipelined CPU/FPU Test; Exercises; Chapter 11: Memory Hierarchy and Virtual Memory Management; 11.1 Memory; 11.2 Cache Memory; 11.3 Virtual Memory Management and TLB Design; 11.4 Mechanism of TLB-Based MIPS Memory Management; Exercises 327 $aChapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL 330 $aUses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few 606 $aVerilog (Computer hardware description language) 606 $aComputer engineering$xData processing 615 0$aVerilog (Computer hardware description language) 615 0$aComputer engineering$xData processing. 676 $a621.390285/5133 700 $aLi$b Yamin$0891991 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910131514203321 996 $aComputer principles and design in Verilog HDL$91992101 997 $aUNINA