LEADER 01044nam0-22003731i-450 001 990002587310403321 005 20200219122812.0 035 $a000258731 035 $aFED01000258731 035 $a(Aleph)000258731FED01 035 $a000258731 100 $a20000920d1969----km-y0itay50------ba 101 0 $afre 102 $aFR 200 1 $aAnalyse de variance et plans d'experiénce$fD. Dugué, M. Girault 205 $a2éme ed 210 $aParis$cDunod$d1969 215 $a132 p.$d24 cm 225 1 $aProbabilites, statistique richerche operationnelle 610 0 $aPianificazioni di indagini 610 0 $aPiano degli esperimenti 676 $a519 700 1$aDugué,$bDaniel$0342391 701 1$aGirault,$bMaurice$041753 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990002587310403321 952 $aXV-A-17$b3420$fMAS 952 $a02 29 B 37$b1433$fFINBN 959 $aFINBN 959 $aMAS 996 $aAnalyse de variance et plans d'expérience$935036 997 $aUNINA DB $aING01 LEADER 05605nam 2200745Ia 450 001 9910131049403321 005 20200520144314.0 010 $a1-283-40527-X 010 $a9786613405272 010 $a1-119-99114-5 010 $a1-119-99113-7 035 $a(CKB)3460000000003397 035 $a(EBL)699356 035 $a(SSID)ssj0000476978 035 $a(PQKBManifestationID)11324981 035 $a(PQKBTitleCode)TC0000476978 035 $a(PQKBWorkID)10480703 035 $a(PQKB)11377755 035 $a(Au-PeEL)EBL699356 035 $a(CaPaEBR)ebr10510714 035 $a(OCoLC)714797081 035 $a(CaSebORM)9781119992653 035 $a(MiAaPQ)EBC699356 035 $a(EXLCZ)993460000000003397 100 $a20101215d2011 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aESD$b[electronic resource] $edesign and synthesis /$fSteven H. Voldman 205 $a1st edition 210 $aChichester, West Sussex, U.K. $cWiley$d2011 215 $a1 online resource (292 p.) 225 1 $aESD series 300 $aDescription based upon print version of record. 311 $a1-119-99265-6 311 $a0-470-68571-9 320 $aIncludes bibliographical references and index. 327 $aESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window 327 $a1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing 327 $a1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE 327 $a1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes 327 $a1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O 327 $a2.2.3 Core-Limited Peripheral I/O Design Architecture 330 $aElectrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach. 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