LEADER 00969nam0-22003131--450- 001 990009370860403321 005 20110601200856.0 035 $a000937086 035 $aFED01000937086 035 $a(Aleph)000937086FED01 035 $a000937086 100 $a20110531d1929----km-y0itay50------ba 101 0 $aita$alat 102 $aIT 105 $aa-------001cd 200 1 $a<>congiura di Catilina$fSallustio$gversione di Enrico Corradini 210 $aLa Santa (Milano)$cSocietā Anonima Notari$d1929 215 $aXI, 154 p.$d23 cm 225 1 $aRomanorum scriptorum corpus italicum$fcurante Hectore Romagnoli 676 $a870.01 700 1$aSallustius Crispus,$bGaius$f<86-ca. 34 a. c.>$0154956 702 1$aCorradini,$bEnrico$f<1865-1931> 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990009370860403321 952 $aIV ZL Sallustio 3$b18138$fFGBC 959 $aFGBC 996 $aCongiura di Catilina$9290743 997 $aUNINA LEADER 01166nam0 22002771i 450 001 SUN0030617 005 20110405101046.504 010 $a89-8128-596- 100 $a20041215d2001 |0engc50 ba 101 $aeng 102 $aGB 105 $a|||| ||||| 200 1 $aDefining a macroeconomic framework for the Euro area$fAlberto Alesina ... [et al.] 210 $aLondon$cCentre for Economic Policy Research$d[2001?] 215 $a50 p.$cill.$d28 cm. 606 $aBanca Centrale Europea$2FI$3SUNC001897 620 $aGB$dLondon$3SUNL000015 702 1$aAlesina$b, Alberto$3SUNV025295 712 02$aCentre for Economic Policy Research$cGreat Britain$3SUNV025294 712 $aCentre for economic policy research$3SUNV001950$4650 801 $aIT$bSOL$c20181109$gRICA 912 $aSUN0030617 950 $aUFFICIO DI BIBLIOTECA DEL DIPARTIMENTO DI GIURISPRUDENZA$d00 CONS X.Ec.34 $e00 21927 995 $aUFFICIO DI BIBLIOTECA DEL DIPARTIMENTO DI GIURISPRUDENZA$h21927$kCONS X.Ec.34$op$qa 996 $aDefining a macroeconomic framework for the Euro area$9693089 997 $aUNICAMPANIA LEADER 01476nam0 22003613i 450 001 MIL0202418 005 20251003044228.0 010 $a0471594466 100 $a20090723d1994 ||||0itac50 ba 101 | $aeng 102 $aus 181 1$6z01$ai $bxxxe 182 1$6z01$an 200 1 $aIntegrated circuit, hybrid, and multichip module package design guidelines$ea focus on reliability$fMichael Pecht 210 $aNew York [etc.]$cWiley$d1994 215 $aXXXI, 426 p. 25 cm. 606 $aCircuiti integrati$xProgettazione$2FIR$3MILC095947$9E 606 $aComponenti elettronici$xMontaggio$2FIR$3CFIC054803$9I 676 $a621.381$9Ingegneria elettronica$v14 676 $a621.381046$9Ingegneria elettronica. Assemblaggio$v22 696 $aChip$aCircuiti elettronici integrati 699 $aCircuiti integrati$yChip 699 $aCircuiti integrati$yCircuiti elettronici integrati 700 1$aPecht$b, Michael$3MILV104044$4070$0719287 790 1$aPecht$b, Michael G.$3MILV157183$zPecht, Michael 801 3$aIT$bIT-000000$c20090723 850 $aIT-BN0095 901 $bNAP 01$cSALA DING $n$ 912 $aMIL0202418 950 0$aBiblioteca Centralizzata di Ateneo$b1 v.$c1 v.$d 01SALA DING 621.381 PEC.in$e 0102 0000018745 VMA A4 1 v.$fY $h19940119$i19940119 977 $a 01 996 $aIntegrated circuit, hybrid, and multichip module package design guidelines$91396328 997 $aUNISANNIO