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102   $aDE
135   $adrnn-008mamaa
200 1 $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$bRisorsa elettronica$e18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers$fedited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, Lars Svensson, José Monteiro
210   $aBerlin ; Heidelberg$cSpringer$d2009
225 1 $aLecture Notes in Computer Science$x0302-9743$v5349
230   $aDocumento elettronico
336   $aTesto
337   $aFormato html, pdf
702  1$aHutchison,$bDavid
702  1$aKanade,$bTakeo
702  1$aKittler,$bJosef
702  1$aKleinberg,$bJon M.
702  1$aMattern,$bFriedemann
702  1$aMitchell,$bJohn C.
702  1$aMonteiro,$bJosé
702  1$aNaor,$bMoni
702  1$aNierstrasz,$bOscar
702  1$aPandu Rangan,$bC.
702  1$aSteffen,$bBernhard
702  1$aSudan,$bMadhu
702  1$aSvensson,$bLars
702  1$aTerzopoulos,$bDemetri
702  1$aTygar,$bDoug
702  1$aVardi,$bMoshe Y.
702  1$aWeikum,$bGerhard
801  0$aIT$bUNINA$gREICAT$2UNIMARC
856 4 $zFull text per gli utenti Federico II$uhttp://dx.doi.org/10.1007/978-3-540-95948-9
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912   $a990009259170403321
961   $aArithmetic and Logic Structures
961   $aCircuits and Systems
961   $aComputer science
961   $aComputer Science
961   $aComputer system performance
961   $aLogic design
961   $aLogic Design
961   $aMemory management (Computer science)
961   $aMemory Structures
961   $aProcessor Architectures
961   $aSystem Performance and Evaluation
961   $aSystems engineering
996   $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$9772134
997   $aUNINA

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