LEADER 00955nam0-22003371i-450- 001 990007515470403321 005 20110204134048.0 035 $a000751547 035 $aFED01000751547 035 $a(Aleph)000751547FED01 035 $a000751547 100 $a20030814d1958----km-y0itay50------ba 101 0 $aita 102 $aIT 105 $ay-------001yy 200 1 $aDieci anni di politica agraria nel Mezzogiorno$fManlio Rossi-Doria 210 $aRoma ; Bari$cLaterza$d1958 215 $a414 p.$d20 cm 225 1 $aLibri del tempo Laterza$v49 610 0 $aMezzogiorno 676 $a333 700 1$aRossi-Doria,$bManlio$f<1905-1988>$034272 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990007515470403321 952 $aXXI Coll. 15 (49)$b53691$fFGBC 952 $aE-02-175$bIst. 6536$fILFGE 959 $aILFGE 959 $aFGBC 996 $aDieci anni di politica agraria nel Mezzogiorno$9683033 997 $aUNINA LEADER 01228nam0-22003371i-450- 001 990005440680403321 005 20100512121307.0 035 $a000544068 035 $aFED01000544068 035 $a(Aleph)000544068FED01 035 $a000544068 100 $a19990604e19671922km-y0itay50------ba 101 0 $agrc$ager 102 $aDE 105 $ay-------001yy 200 1 $aNamenbuch$eenthaltend alle griechischen, lateinischen, ägyptischen, hebräischen, arabischen und sonstigen semitischen und nichtsemitischen Menschennamen, soweit sie in griechischen Urkunden (Papyri, Ostraka, Inschriften, Mumienschildern usw) Ägyptens sich vorfinden$fbearbeit und herausgegeben von Friedrich Preisigke 205 $aRist. 210 $aAmsterdam$cAdolf M. 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Introduction; Chapter 2. Model Validation; 2.1 Platform versus System Behavior; 2.2 Criteria for Design Model; 2.3 Informal Requirements: A Case Study; 2.3.1 The Requirements Document; 2.3.2 Simplification of the Informal Requirements; 2.4 Common Modeling Notations; 2.4.1 Finite-State Machines; 2.4.2 Communicating FSMs; 2.4.3 Message Sequence Chart-Based Models; 2.5 Remarks About Modeling Notations; 2.6 Model Simulations; 2.6.1 FSM Simulations 327 $a2.6.2 Simulating MSC-Based System Models2.7 Model-Based Testing; 2.8 Model Checking; 2.8.1 Property Specification; 2.8.2 Checking Procedure; 2.9 The SPIN Validation Tool; 2.10 The SMV Validation Tool; 2.11 Case Study: Air-Traffic Controller; 2.12 References; 2.13 Exercises; Chapter 3. Communication Validation; 3.1 Common Incompatibilities; 3.1.1 Sending/Receiving Signals in Different Order; 3.1.2 Handling a Different Signal Alphabet; 3.1.3 Mismatch in Data Format; 3.1.4 Mismatch in Data Rates; 3.2 Converter Synthesis; 3.2.1 Representing Native Protocols and Converters 327 $a3.2.2 Basic Ideas for Converter Synthesis3.2.3 Various Strategies for Protocol Conversion; 3.2.4 Avoiding No-Progress Cycles; 3.2.5 Speculative Transmission to Avoid Deadlocks; 3.3 Changing a Working Design; 3.4 References; 3.5 Exercises; Chapter 4. Performance Validation; 4.1 The Conventional Abstraction of Time; 4.2 Predicting Execution Time of a Program; 4.2.1 WCET Calculation; 4.2.2 Modeling of Microarchitecture; 4.3 Interference within a Processing Element; 4.3.1 Interrupts from Environment; 4.3.2 Contention and Preemption; 4.3.3 Sharing a Processor Cache 327 $a4.4 System-Level Communication Analysis4.5 Designing Systems with Predictable Timing; 4.5.1 Scratchpad Memories; 4.5.2 Time-Triggered Communication; 4.6 Emerging Applications; 4.7 References; 4.8 Exercises; Chapter 5. Functionality Validation; 5.1 Dynamic or Trace-Based Checking; 5.1.1 Dynamic Slicing; 5.1.2 Fault Localization; 5.1.3 Directed Testing Methods; 5.2 Formal Verification; 5.2.1 Predicate Abstraction; 5.2.2 Software Checking via Predicate Abstraction; 5.2.3 Combining Formal Verification with Testing; 5.3 References; 5.4 Exercises; Bibliography; Index 330 $a Modern embedded systems require high performance, low cost and low power consumption. Such systems typically consist of a heterogeneous collection of processors, specialized memory subsystems, and partially programmable or fixed-function components. This heterogeneity, coupled with issues such as hardware/software partitioning, mapping, scheduling, etc., leads to a large number of design possibilities, making performance debugging and validation of such systems a difficult problem. Embedded systems are used to control safety critical applications such as flight control, automotive el 410 0$aMorgan Kaufmann series in systems on silicon. 606 $aEmbedded computer systems$xDesign and construction 606 $aEmbedded computer systems$xTesting 606 $aComputer software$xTesting 615 0$aEmbedded computer systems$xDesign and construction. 615 0$aEmbedded computer systems$xTesting. 615 0$aComputer software$xTesting. 676 $a004.1 700 $aRoychoudhury$b Abhik$01823890 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9911006781103321 996 $aEmbedded systems and software validation$94390832 997 $aUNINA