LEADER 01291nam0-22003971i-450- 001 990007144520403321 005 20110909125433.0 010 $a88-15-05785-4 035 $a000714452 035 $aFED01000714452 035 $a(Aleph)000714452FED01 035 $a000714452 100 $a20110909d1997----km-y0itay50------ba 101 0 $aita 102 $aIT 105 $ay-------001yy 200 1 $aCavalieri e fanti$eproposte e proponenti nelle elezioni del 1994 e del 1996$fa cura di Piergiorgio Corbetta e Arturo M.L. Parisi 210 $aBologna$cil Mulino$d1997 215 $a421 p.$d22 cm 225 1 $aRicerche e studi dell'Istituto Cattaneo 225 1 $a<>transizione politica italiana 300 $aIn testa al front.: Istituto di studi e ricerche Carlo Cattaneo 610 0 $aElezioni politiche$aItalia$a1994-1996 676 $a324.630 945$v21$zita 702 1$aCorbetta,$bPiergiorgio$f<1941- > 702 1$aParisi,$bArturo M. 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Smith$gforeword by Lord Boyd Orr 210 $aEdinburgh$cOliver & Boyd$d1972 215 $aXII, 126 p.$cill.$d22 cm 610 0 $aNutrizione$aAspetti sociali 676 3$a53.56$v23$zita 702 1$aSmith,$bGeorge 702 1$aSmith,$bJohn C. 801 0$aIT$bUNINA$gREICAT$2UNIMARC 901 $aBK 912 $a990001451460403321 952 $aBSF 353.56 SMI 1$b218$fSC1 959 $aSC1 996 $aBiology of Affluence$9373692 997 $aUNINA LEADER 04554nam 22005895 450 001 9910366582703321 005 20251116220338.0 010 $a3-030-24737-6 024 7 $a10.1007/978-3-030-24737-9 035 $a(CKB)4100000009523002 035 $a(DE-He213)978-3-030-24737-9 035 $a(MiAaPQ)EBC5939528 035 $a(PPN)258876115 035 $a(EXLCZ)994100000009523002 100 $a20191009d2020 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aSystem Verilog Assertions and Functional Coverage $eGuide to Language, Methodology and Applications /$fby Ashok B. Mehta 205 $a3rd ed. 2020. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2020. 215 $a1 online resource (XXXIX, 507 p. 270 illus., 258 illus. in color.) 300 $aIncludes index. 311 08$a3-030-24736-8 327 $aIntroduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions ? Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- ?expect? -- ?assume? and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800?2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions ? LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options. 330 $aThis book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ?have we functionally verified everything?. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. · Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; · Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; · Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; · Explains each concept in a step-by-step fashion and applies it to a practical real life example; · Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book. 606 $aElectronic circuits 606 $aElectronics 606 $aMicroelectronics 606 $aMicroprocessors 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 615 0$aElectronic circuits. 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aMicroprocessors. 615 14$aCircuits and Systems. 615 24$aElectronics and Microelectronics, Instrumentation. 615 24$aProcessor Architectures. 676 $a621.3815 676 $a621.392 700 $aMehta$b Ashok B.$4aut$4http://id.loc.gov/vocabulary/relators/aut$0763798 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910366582703321 996 $aSystem Verilog assertions and functional coverage$92215558 997 $aUNINA