LEADER 01030nam0-22003611i-450- 001 990001357280403321 010 $a0-8218-0282-8 035 $a000135728 035 $aFED01000135728 035 $a(Aleph)000135728FED01 035 $a000135728 100 $a20000920d1996----km-y0itay50------ba 101 0 $aeng 200 1 $aLectures on entire functions$fB. Ya. Levin 210 $aProvidence (RI)$cAmerican Mathematical Society$dc1996 215 $axv, 248 p.$cill.$d26 cm 225 1 $aTranslations of mathematical monographs$v150 610 0 $aFunzioni di variabile complessa 676 $a515.98 700 1$aLevin,$bBoris Yakovlevich$0350938 702 1$aLyubarskii,$bYu. 702 1$aSodin,$bM. 702 1$aTkachenko,$bVadim$f<1937- > 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990001357280403321 952 $aC-29-(150$b15031$fMA1 959 $aMA1 962 $a30DXX 962 $a30D20 996 $aLectures on entire functions$9375776 997 $aUNINA DB $aING01 LEADER 01364nam--2200409---450- 001 990000539420203316 005 20090611123401.0 010 $a88-387-1889-X 035 $a0053942 035 $aUSA010053942 035 $a(ALEPH)000053942USA01 035 $a0053942 100 $a20010703d2001----km-y0itay0103----ba 101 $aita 102 $aIT 105 $a||||||||001yy 200 1 $a<> disciplina del subappalto nell'ambito dei lavori pubblici$econ CD-ROM contenente gli schemi di provvedimento$fMichele Pini 210 $aRimini$cMaggioli$dcopyr.2001 215 $a203 p.$d24 cm$eCD-ROM 225 2 $aAppalti & lavori pubblici 300 $aSegue: Appendice normativa 410 0$12001$aAppalti & lavori pubblici 606 $aLavori pubblici$xSubappalti$xLegislazione 676 $a344.4506 700 1$aPINI,$bMichele$0546249 801 0$aIT$bsalbc$gISBD 912 $a990000539420203316 951 $aXXIV.3.H 47 (IG V 733)$b30039 G.$cXXIV.3.H 47 (IG V)$d00075282 959 $aBK 969 $aGIU 979 $aANGELA$b90$c20010703$lUSA01$h1249 979 $aANGELA$b90$c20010703$lUSA01$h1252 979 $c20020403$lUSA01$h1703 979 $aPATRY$b90$c20040406$lUSA01$h1637 979 $aRSIAV5$b90$c20090611$lUSA01$h1234 996 $aDisciplina del subappalto nell'ambito dei lavori pubblici$9885702 997 $aUNISA LEADER 04671nam 22006255 450 001 9910377818103321 005 20250609111816.0 010 $a3-030-38796-8 024 7 $a10.1007/978-3-030-38796-9 035 $a(CKB)4100000010480444 035 $a(DE-He213)978-3-030-38796-9 035 $a(MiAaPQ)EBC6126766 035 $a(PPN)242981968 035 $a(MiAaPQ)EBC6126455 035 $a(EXLCZ)994100000010480444 100 $a20200227d2020 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling $eFrom the Clock Path to the Data Path /$fby Saurabh Jain, Longyang Lin, Massimo Alioto 205 $a1st ed. 2020. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2020. 215 $a1 online resource (XVI, 168 p. 113 illus., 107 illus. in color.) 311 08$a3-030-38795-X 327 $aIntroduction to wide voltage scaling, applications and challenges -- Reconfigurable microarchitectures down to pipestage and memory bank level -- Automated design flows and run-time optimization for reconfigurable microarchitectures -- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories -- Reconfigurable clock networks, automated design flows, run-time optimization and case study -- Conclusion. 330 $aThis book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained. Provides extensive coverage of the challenges and the key technologies enabling wide power-performance range in digital sub-systems (e.g., processors, memories, accelerators); Includes in-depth description of silicon-proven methodologies to design reconfigurable data path and clock path; Describes techniques for reconfigurable microarchitectures, down to the pipestage and the clock repeater level; Uses a highly interdisciplinary approach covering the circuit, the microarchitectural and the system levels of abstraction; Presents practical design examples and the related methodologies; Offers complementary design files and scripts, useful to replicate the presented developments and develop new designs. 606 $aElectronic circuits 606 $aComputer engineering 606 $aInternet of things 606 $aEmbedded computer systems 606 $aMicroprocessors 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aCyber-physical systems, IoT$3https://scigraph.springernature.com/ontologies/product-market-codes/T24080 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 615 0$aElectronic circuits. 615 0$aComputer engineering. 615 0$aInternet of things. 615 0$aEmbedded computer systems. 615 0$aMicroprocessors. 615 14$aCircuits and Systems. 615 24$aCyber-physical systems, IoT. 615 24$aProcessor Architectures. 676 $a621.381 700 $aJain$b Saurabh$4aut$4http://id.loc.gov/vocabulary/relators/aut$0935196 702 $aLin$b Longyang$4aut$4http://id.loc.gov/vocabulary/relators/aut 702 $aAlioto$b Massimo$4aut$4http://id.loc.gov/vocabulary/relators/aut 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910377818103321 996 $aAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling$92106239 997 $aUNINA