LEADER 00717nam0-22002531i-450- 001 990001219720403321 035 $a000121972 035 $aFED01000121972 035 $a(Aleph)000121972FED01 035 $a000121972 100 $a20000920d--------km-y0itay50------ba 101 0 $aeng 200 1 $aProof Methods for Modal and Intuitionistic Logics$fby Fitting M. 210 $aBoston [etc.]$cReidel 225 1 $aSynthese Library$v169 700 1$aFitting,$bMelvin$046831 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990001219720403321 952 $aC-25-(169$b369$fMA1 959 $aMA1 996 $aProof Methods for Modal and Intuitionistic Logics$9343155 997 $aUNINA DB $aING01 LEADER 03533oam 2200421zu 450 001 9910142188403321 005 20241212215350.0 010 $a9781509097258 010 $a1509097252 035 $a(CKB)1000000000036025 035 $a(SSID)ssj0000453730 035 $a(PQKBManifestationID)12203628 035 $a(PQKBTitleCode)TC0000453730 035 $a(PQKBWorkID)10486352 035 $a(PQKB)11345545 035 $a(NjHacI)991000000000036025 035 $a(EXLCZ)991000000000036025 100 $a20160829d2005 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 00$a2005 IEEE International High Level Design Validation and Test Workshop 210 31$a[Place of publication not identified]$cI E E E$d2005 215 $a1 online resource (viii, 250 pages) $cillustrations 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9780780395718 311 08$a0780395719 327 $aSimulation-based functional test generation for embedded processors,"C. -- Scalable defect mapping and configuration of memory-based nanofabrics,"Chen -- Improvement of fault injection techniques based on VHDL code modification,"J. -- MVP: a mutation-based validation paradigm,"J. -- Establishing latch correspondence for embedded circuits of PowerPC microprocessors,"H. -- Sequential equivalence checking based on k-th invariants and circuit SAT solving,"Feng -- VERISEC: verifying equivalence of sequential circuits using SAT,"M. -- Automated clock inference for stream function-based system level specifications,"J. -- Cosimulation of ITRON-based embedded software with SystemC,"S. -- A software test program generator for verifying system-on-chips,"A. -- Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model,"Che-Hua -- DVGen: a test generator for the transmeta Efficeon VLIW processor,"K. -- Reuse in system-level stimuli-generation,"Y. -- Harnessing machine learning to improve the success rate of stimuli generation,"S. -- A new simulation-based property checking algorithm based on partitioned alternative search space traversal,"Qingwei -- Validating families of latency insensitive protocols,"S. -- GASIM: a fast Galois field based simulator for functional model,"D. -- Overlap reduction in symbolic system traversal,"P. -- Formal verification of high-level conformance with symbolic simulation,"R. -- A method for generation of GSTE assertion graphs,"E. -- Automatic abstraction refinement for Petri nets verification,"Zhenyu -- An optimum algorithm for compacting error traces for efficient functional debugging,"Chia-Chih -- Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking,"V. -- B-cubing theory: new possibilities for efficient SAT-solving,"D. -- Multilevel design validation in a secure embedded system,"D. -- Security evaluation against electromagnetic analysis at design time,"Huiyun -- Formal meaning of coverage metrics in simulation-based hardware design verification,"I. -- Advanced analysis techniques for cross-product coverage,"H. -- A proof of correctness for the construction of property monitors,". 606 $aComputer software$xVerification$vCongresses 615 0$aComputer software$xVerification 676 $a005.14 801 0$bPQKB 906 $aPROCEEDING 912 $a9910142188403321 996 $a2005 IEEE International High Level Design Validation and Test Workshop$92341855 997 $aUNINA