LEADER 01342nam 2200361Ia 450 001 996387367203316 005 20221108083347.0 035 $a(CKB)1000000000632225 035 $a(EEBO)2240869475 035 $a(OCoLC)52211918 035 $a(EXLCZ)991000000000632225 100 $a20030509d1699 uy 0 101 0 $aeng 135 $aurbn||||a|bb| 200 04$aThe case of Mr. Daniel Gwyn, agent for the Spanish pacquet-boats$b[electronic resource] $ein relation to Mr. John Russel's charge against him for pretended mismanagement in that imploy 210 $a[London $cs.n.$d1699] 215 $a1 sheet ([2] p.) 300 $aCaption title. 300 $aPublication data suggested by Wing. 300 $aMs. notes in margins; also, portion of text lined through, with handwritten comments below. 300 $aImperfect: stained and creased with some loss of text. 300 $aReproduction of the original in the Lincoln's Inn Library. 330 $aeebo-0082 606 $aFraud$zEngland$vEarly works to 1800 608 $aBroadsides$zEngland$y17th century.$2rbgenr 615 0$aFraud 701 $aGwyn$b Daniel$01020871 801 0$bEAE 801 1$bEAE 906 $aBOOK 912 $a996387367203316 996 $aThe case of Mr. Daniel Gwyn, agent for the Spanish pacquet-boats$92416441 997 $aUNISA LEADER 01257nam0 22003133i 450 001 UFI0436974 005 20231121125909.0 010 $a3631361718 100 $a20160219d2000 ||||0itac50 ba 101 | $aeng 102 $ade 181 1$6z01$ai $bxxxe 182 1$6z01$an 200 1 $aBecoming loquens$emore studies in language origins$fedited by Bernard H. Bichakjian ... °et al.! 210 $aFrankfurt am Main °etc.!$cPeter Lang$d2000 215 $aXII, 385 p.$d21 cm. 225 | $aBochum publications in evolutionary cultural semiotics. New series$v1 410 0$1001UFI0450924$12001 $aBochum publications in evolutionary cultural semiotics. New series$v1 606 $aLinguaggio$xOrigini$2FIR$3RMLC141831$9I 676 $a401$9Linguaggio. Filosofia e teoria$v21 702 1$aBichakjian$b, Bernard H.$3UBOV378645 801 3$aIT$bIT-01$c20160219 850 $aIT-FR0017 899 $aBiblioteca umanistica Giorgio Aprea$bFR0017 912 $aUFI0436974 950 0$aBiblioteca umanistica Giorgio Aprea$d 52CIS 11/77$e 52VM 0000672975 VM barcode:00043990. - Inventario:756 FSCVM$fA $h20070309$i20121204 977 $a 52 996 $aBecoming loquens$93641953 997 $aUNICAS LEADER 05846nam 2200745 450 001 9910780935303321 005 20230125221255.0 010 $a1-59693-425-5 035 $a(CKB)2550000000002726 035 $a(EBL)946534 035 $a(OCoLC)796382975 035 $a(SSID)ssj0000397890 035 $a(PQKBManifestationID)11292847 035 $a(PQKBTitleCode)TC0000397890 035 $a(PQKBWorkID)10362518 035 $a(PQKB)11255740 035 $a(Au-PeEL)EBL946534 035 $a(CaPaEBR)ebr10359035 035 $a(CaBNVSL)mat09100288 035 $a(IEEE)9100288 035 $a(MiAaPQ)EBC946534 035 $a(EXLCZ)992550000000002726 100 $a20200729d2009 uy 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aMetamodeling-driven IP reuse for SoC integration and microprocessor design /$fDeepak A. Mathaikutty, Sandeep K. Shukla 210 1$aBoston :$cArtech House,$d©2009. 210 2$a[Piscataqay, New Jersey] :$cIEEE Xplore,$d[2009] 215 $a1 online resource (310 p.) 300 $aDescription based upon print version of record. 311 $a1-59693-424-7 320 $aIncludes bibliographical references and index. 327 $aMetamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider 327 $aSupport for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation 327 $a2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION 327 $a3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection 327 $a5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY 327 $a6.5 SUMMARY 330 3 $aThis cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The book covers the essential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a "write once, use many times" verification strategy - another effective approach that can attain a faster product design cycle.$cPublisher abstract. 606 $aComputer software$xReusability 606 $aComputer software$xVerification 606 $aIntellectual property 606 $aMicroprocessors$xDesign and construction 606 $aSystem design 606 $aSystems on a chip$xDesign and construction 615 0$aComputer software$xReusability. 615 0$aComputer software$xVerification. 615 0$aIntellectual property. 615 0$aMicroprocessors$xDesign and construction. 615 0$aSystem design. 615 0$aSystems on a chip$xDesign and construction. 676 $a621.39 676 $a621.3916 700 $aMathaikutty$b Deepak A.$01580356 701 $aShukla$b Sandeep K$01580357 801 0$bCaBNVSL 801 1$bCaBNVSL 801 2$bCaBNVSL 906 $aBOOK 912 $a9910780935303321 996 $aMetamodeling-driven IP reuse for SoC integration and microprocessor design$93861238 997 $aUNINA