LEADER 01316nam2 22003253i 450 001 UBO1431981 005 20231121125856.0 100 $a20030422d1968 ||||0itac50 ba 101 | $aita$agrc 102 $ait 181 1$6z01$ai $bxxxe 182 1$6z01$an 200 0 $a1: Libri 1.-2 210 $aNapoli$cLoffredo$d1968 215 $aXII, 175 p.$d20 cm. 461 1$1001RAV0164464$12001 $a˜Le œArgonautiche$fApollonio Rodio$gtesto, traduzione e note a cura di Giuseppe Pompella$v1 700 0$aApollonius : Rhodius$3CFIV051236$4070$0259531 702 1$aPompella$b, Giuseppe$3CFIV039271$4340 790 0$aApollonius Rhodius$3CFIV051237$zApollonius : Rhodius 790 0$aApollonio : Rodio$3CFIV051238$zApollonius : Rhodius 801 3$aIT$bIT-01$c20030422 850 $aIT-RM0289 $aIT-RM0418 $aIT-FR0017 899 $aBiblioteca Statale A. Baldini$bRM0289 899 $aBIBLIOTECA ACCADEMIA NAZ. DEI LINCEI E CORSINIANA$bRM0418 899 $aBiblioteca umanistica Giorgio Aprea$bFR0017 $eN 912 $aUBO1431981 950 2$aBiblioteca umanistica Giorgio Aprea$d 52DFA F 3.1$e 52FLS0000320765 VMB RS $fC $h20151002$i20151002 977 $a 04$a 10$a 52 996 $a1: Libri 1.-2$93640221 997 $aUNICAS LEADER 03302nam 22005295 450 001 9910337645003321 005 20200630220158.0 010 $a3-030-03238-8 024 7 $a10.1007/978-3-030-03238-8 035 $a(CKB)4100000007223587 035 $a(MiAaPQ)EBC5620202 035 $a(DE-He213)978-3-030-03238-8 035 $a(PPN)232967040 035 $a(EXLCZ)994100000007223587 100 $a20181214d2019 u| 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aLearning from VLSI Design Experience /$fby Weng Fook Lee 205 $a1st ed. 2019. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2019. 215 $a1 online resource (xxix, 214 pages) 311 $a3-030-03237-X 327 $aChapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage. . 330 $aThis book shares with readers practical design knowledge gained from the author?s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds. Addresses practical design issues and their workarounds; Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine; Provides readers with an RTL coding guideline, based on real experience. 606 $aElectronic circuits 606 $aMicroprocessors 606 $aElectronics 606 $aMicroelectronics 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a621.395 700 $aLee$b Weng Fook$4aut$4http://id.loc.gov/vocabulary/relators/aut$0867193 906 $aBOOK 912 $a9910337645003321 996 $aLearning from VLSI Design Experience$91935535 997 $aUNINA