LEADER 01088nam0 22002773i 450 
001 VAN0246179
005 20220524123043.73
017 70$2N$a978-981-33-4642-0
100   $a20220520d2021       |0itac50      ba
101   $aeng
102   $aSG
105   $a||||    |||||
200 1 $aASIC Design and Synthesis$eRTL Design Using Verilog$fVaibbhav Taraate
210   $aSingapore$cSpringer$d2021
215   $aXXI, 330 p.$cill.$d24 cm
620   $aSG$dSingapore$3VANL000061
700  1$aTaraate$bVaibbhav$3VANV091912$0788080
712   $aSpringer <editore>$3VANV108073$4650
801   $aIT$bSOL$c20240614$gRICA
856 4 $uhttps://link.springer.com/book/10.1007/978-981-33-4642-0$zE-book ? Accesso al full-text attraverso riconoscimento IP di Ateneo, proxy e/o Shibboleth
899   $aBIBLIOTECA CENTRO DI SERVIZIO SBA$2VAN15
912   $fN
912   $aVAN0246179
950   $aBIBLIOTECA CENTRO DI SERVIZIO SBA$d15CONS      SBA EBOOK 9113                      $e15EB 9113              20220520            
996   $aASIC design and synthesis$92849475
997   $aUNICAMPANIA