05861nam 22007455 450 99646586090331620230406032333.010.1007/11560548(CKB)1000000000213281(SSID)ssj0000317038(PQKBManifestationID)11240581(PQKBTitleCode)TC0000317038(PQKBWorkID)10295905(PQKB)10067688(DE-He213)978-3-540-32030-2(MiAaPQ)EBC3067864(PPN)123097800(EXLCZ)99100000000021328120100319d2005 u| 0engurnn|008mamaatxtccrCorrect Hardware Design and Verification Methods[electronic resource] 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings /edited by Dominique Borrione, Wolfgang Paul1st ed. 2005.Berlin, Heidelberg :Springer Berlin Heidelberg :Imprint: Springer,2005.1 online resource (XII, 414 p.) Theoretical Computer Science and General Issues,2512-2029 ;3725Bibliographic Level Mode of Issuance: Monograph3-540-32030-X 3-540-29105-9 Includes bibliographical references and index.Invited Talks -- Is Formal Verification Bound to Remain a Junior Partner of Simulation? -- Verification Challenges in Configurable Processor Design with ASIP Meister -- Tutorial -- Towards the Pervasive Verification of Automotive Systems -- Functional Approaches to Design Description -- Wired: Wire-Aware Circuit Design -- Formalization of the DE2 Language -- Game Solving Approaches -- Finding and Fixing Faults -- Verifying Quantitative Properties Using Bound Functions -- Abstraction -- How Thorough Is Thorough Enough? -- Interleaved Invariant Checking with Dynamic Abstraction -- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units -- Algorithms and Techniques for Speeding (DD-Based) Verification 1 -- Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting -- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation -- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning -- Real Time and LTL Model Checking -- Real-Time Model Checking Is Really Simple -- Temporal Modalities for Concisely Capturing Timing Diagrams -- Regular Vacuity -- Algorithms and Techniques for Speeding Verification 2 -- Automatic Generation of Hints for Symbolic Traversal -- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies -- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation -- Evaluation of SAT-Based Tools -- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment -- Model Reduction -- Exploiting Constraints in Transformation-Based Verification -- Identification and Counter Abstraction for Full Virtual Symmetry -- Verification of Memory Hierarchy Mechanisms -- On the Verification of Memory Management Mechanisms -- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification -- Short Papers -- Symbolic Partial Order Reduction for Rule Based Transition Systems -- Verifying Timing Behavior by Abstract Interpretation of Executable Code -- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths -- Deadlock Prevention in the Æthereal Protocol -- Acceleration of SAT-Based Iterative Property Checking -- Error Detection Using BMC in a Parallel Environment -- Formal Verification of Synchronizers -- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems -- Improvements to the Implementation of Interpolant-Based Model Checking -- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design -- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic -- Resolving Quartz Overloading -- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers -- Predictive Reachability Using a Sample-Based Approach -- Minimizing Counterexample of ACTL Property -- Data Refinement for Synchronous System Specification and Construction -- Introducing Abstractions via Rewriting -- A Case Study: Formal Verification of Processor Critical Properties.Theoretical Computer Science and General Issues,2512-2029 ;3725Computer scienceComputersSoftware engineeringMachine theoryArtificial intelligenceTheory of ComputationComputer HardwareComputer Science Logic and Foundations of ProgrammingSoftware EngineeringFormal Languages and Automata TheoryArtificial IntelligenceComputer science.Computers.Software engineering.Machine theory.Artificial intelligence.Theory of Computation.Computer Hardware.Computer Science Logic and Foundations of Programming.Software Engineering.Formal Languages and Automata Theory.Artificial Intelligence.621.39/5Borrione Dominiqueedthttp://id.loc.gov/vocabulary/relators/edtPaul Wolfgangedthttp://id.loc.gov/vocabulary/relators/edtIFIP WG 10.5.BOOK996465860903316Correct Hardware Design and Verification Methods772373UNISA01935nam0 22003611i 450 RER003694520251003044334.020180829d1992 ||||0itac50 baitaitz01i xxxe z01nz01ncRDAcarrierParere del Comitato Nazionale per la Bioetica sulla proposta di risoluzione sull'assistenza ai pazienti terminaliapprovata dalla Commissione per la protezione dell'ambiente, sanità pubblica e tutela dei consumatori del Parlamento Europeo 30 aprile 1991Comitato Nazionale per la BioeticaRoma Presidenza del Consiglio dei Ministri Dipartimento per l'informazione e l'editoria[1992?]61 p.24 cm.Società e istituzioni001CFI00301772001 Società e istituzioniBioeticaFIRCFIC066886E174.957ETICA DI ALTRE PROFESSIONI E OCCUPAZIONI. Persone operanti nelle scienze della vita21Comitato nazionale per la bioeticaIEIV027940070295169Italian National Bioethics CommitteeIEIV098326Comitato nazionale per la bioeticaNational Bioetchics CommitteeIEIV098327Comitato nazionale per la bioeticaItalian National Bioethics CommitteeIEIV098326Comitato nazionale per la bioeticaNational Bioetchics CommitteeIEIV098327Comitato nazionale per la bioeticaITIT-00000020180829IT-BN0095 NAP 01D $RER0036945Biblioteca Centralizzata di Ateneo 01D (AR) 13 220 01AR 0700132205 VMA 1 v.Y 2018082920180829 01Parere del Comitato Nazionale per la Bioetica sulla proposta di risoluzione sull'assistenza ai pazienti terminali1525669UNISANNIO